Patents by Inventor Panayotis Constantinou Andricacos
Panayotis Constantinou Andricacos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7212091Abstract: A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.Type: GrantFiled: February 8, 2005Date of Patent: May 1, 2007Assignee: International Business Machines CoprorationInventors: Panayotis Constantinou Andricacos, L. Paivikki Buchwalter, Hariklia Deligianni, Robert A. Groves, Christopher Jahnes, Jennifer L. Lund, Michael Meixner, David Earle Seeger, Timothy D. Sullivan, Ping-Chuan Wang
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Patent number: 6946716Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: GrantFiled: February 9, 2004Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Harikilia Deligianni, John Owen Dukovic, Daniel C. Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth P. Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
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Patent number: 6876282Abstract: A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.Type: GrantFiled: May 17, 2002Date of Patent: April 5, 2005Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, L. Paivikki Buchwalter, Hariklia Deligianni, Robert A. Groves, Christopher Jahnes, Jennifer L. Lund, Michael Meixner, David Earle Seeger, Timothy D. Sullivan, Ping-Chuan Wang
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Publication number: 20040229456Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: ApplicationFiled: February 9, 2004Publication date: November 18, 2004Applicant: International Business MachinesInventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
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Patent number: 6709562Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: GrantFiled: July 6, 1999Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
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Publication number: 20030214373Abstract: A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Panayotis Constantinou Andricacos, L. Paivikki Buchwalter, Hariklia Deligianni, Robert A. Groves, Christopher Jahnes, Jennifer L. Lund, Michael Meixner, David Earle Seeger, Timothy D. Sullivan, Ping-Chuan Wang
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Patent number: 6589874Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by different methods such as ion implantation, annealing and diffusion.Type: GrantFiled: July 26, 2001Date of Patent: July 8, 2003Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., Christopher Carr Parks, Kenneth Parker Rodbell, Roger Yen-Luen Tsai
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Patent number: 6570255Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.Type: GrantFiled: July 8, 2002Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., John Michael Cotte, Lynne Gignac, Wilma Jean Horkans, Kenneth Parker Rodbell
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Publication number: 20020171151Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.Type: ApplicationFiled: July 8, 2002Publication date: November 21, 2002Applicant: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, John Michael Cotte, Lynne Gignac, Wilma Jean Horkans, Kenneth Parker Rodbell
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Publication number: 20020115292Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle.Type: ApplicationFiled: July 26, 2001Publication date: August 22, 2002Applicant: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Christopher Carr Parks, Kenneth Parker Rodbell, Roger Yen-Luen Tsai
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Publication number: 20020105082Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer. The first metal and the second metal may be the same or different. A commonly used first metal and second metal may be copper. The present invention may further be carried out by depositing a seed layer of a first metal into an interconnect opening at a thickness of at least 0.Type: ApplicationFiled: January 4, 2001Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, John Michael Cotte, Lynne Gignac, Wilma Jean Horkans, Kenneth Parker Rodbell
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Patent number: 6429523Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.Type: GrantFiled: January 4, 2001Date of Patent: August 6, 2002Assignee: International Business Machines Corp.Inventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., John Michael Cotte, Lynne Gignac, Wilma Jean Horkans, Kenneth Parker Rodbell
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Patent number: 6406608Abstract: An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.Type: GrantFiled: August 2, 2000Date of Patent: June 18, 2002Assignee: International Business Machines CorporationInventors: Cyprian Emeka Uzoh, Wilma Jean Horkans, Panayotis Constantinou Andricacos
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Patent number: 6391773Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.Type: GrantFiled: December 9, 2000Date of Patent: May 21, 2002Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., Roy Carruthers, Alfred Grill, Katherine Lynn Saenger
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Patent number: 6268291Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle.Type: GrantFiled: December 3, 1998Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., Christopher Carr Parks, Kenneth Parker Rodbell, Roger Yen-Luen Tsai
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Publication number: 20010000926Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.Type: ApplicationFiled: December 9, 2000Publication date: May 10, 2001Inventors: Panayotis Constantinou Andricacos, Cyril Cabral, Roy Carruthers, Alfred Grill, Katherine Lynn Saenger
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Patent number: 6224690Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.Type: GrantFiled: March 12, 1996Date of Patent: May 1, 2001Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang, Keith Thomas Kwietniak, Gangadhara Swami Mathad, Sampath Purushothaman, Leathen Shi, Ho-Ming Tong
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Patent number: 6188120Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.Type: GrantFiled: February 24, 1997Date of Patent: February 13, 2001Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., Roy Carruthers, Alfred Grill, Katherine Lynn Saenger
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Patent number: 6113769Abstract: An apparatus for monitoring and adding solution to a plating bath and controlling the quality of deposited metal. At least one monitor monitors at least one condition within a plating bath and produces at least one signal corresponding to the at least one condition. At least one controller receives the at least one signal produced by the at least one monitor, processes the at least one signal, determines whether an additional amount of at least one chemical should be added to the plating bath, and controls at least one valve for controlling flow of the additional amount of the at least one chemical. A pre-mix tank pre-mixes chemicals to be added to the tank. A plurality of holding tanks holds chemicals and supplies the chemicals to the pre-mix tank. At least one valve is arranged between each holding tank and the pre-mix tank. At least one valve is also arranged between the pre-mix tank and the plating bath.Type: GrantFiled: November 21, 1997Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventors: Cyprian Emeka Uzoh, Wilma Jean Horkans, Panayotis Constantinou Andricacos
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Patent number: 6090710Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.Type: GrantFiled: August 15, 1997Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, James McKell Edwin Harper, Chao-Kun Hu, Dale Jonathan Pearson, Scott Kevin Reynolds, King-Ning Tu, Cyprian Emeka Uzoh