Patents by Inventor Pandi Marimuthu

Pandi Marimuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070284726
    Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
    Type: Application
    Filed: August 23, 2007
    Publication date: December 13, 2007
    Inventors: Yaojian Lin, Pandi Marimuthu
  • Publication number: 20070235878
    Abstract: An integrated circuit package system is provided providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon, depositing a first metal layer on the passivation layer and the final metal layer, forming an analog circuit in the first metal layer, coating a first insulation layer on the first metal layer and the passivation layer, exposing a first pad and a second pad of the first metal layer through the first insulation layer, and connecting a first interconnect on the first pad and a second interconnect on the second pad.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 11, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Pandi Marimuthu
  • Publication number: 20070114634
    Abstract: An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer and a silicide layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer and the silicide layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 24, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Yaojian Lin, Haijing Cao, Robert Frye, Pandi Marimuthu
  • Publication number: 20070114651
    Abstract: An integrated circuit stacking system is provided including fabricating an integrated passive device including: providing a semiconductor substrate, forming an integrated inductor, a resistor block, or an integrated capacitor integrated on the semiconductor substrate, and forming contact pads, on the semiconductor substrate, coupled to the integrated inductor, the resistor block, or the integrated capacitor; positioning an integrated circuit die for maintaining an inductor spacing; mounting the integrated circuit die on the integrated passive device; and encapsulating the integrated circuit die and the integrated passive device.
    Type: Application
    Filed: October 4, 2006
    Publication date: May 24, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Pandi Marimuthu, Robert Frye, Yaojian Lin
  • Publication number: 20070080437
    Abstract: An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.
    Type: Application
    Filed: September 22, 2005
    Publication date: April 12, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Pandi Marimuthu, Il Shim
  • Publication number: 20060175689
    Abstract: A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.
    Type: Application
    Filed: February 8, 2005
    Publication date: August 10, 2006
    Applicant: STATS CHIPPAC LTD.
    Inventors: Il Kwon Shim, Seng Guan Chow, Jeffrey Punzalan, Pandi Marimuthu
  • Publication number: 20050263861
    Abstract: An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.
    Type: Application
    Filed: December 8, 2004
    Publication date: December 1, 2005
    Applicant: STATS ChipPAC Ltd.
    Inventors: Byung Ahn, Pandi Marimuthu