Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.

Abstract: A system is provided. The system generally includes a first processor configured to receive image input data from a red-green-blue infrared (RGBIR) sensor. The first processor of the system is configured to generate a first intermediate image data from the image input data. The system generally includes a second processor. The second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (RGB) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (IR) image data from the first intermediate image data. The system generally includes a third processor. The third processor of the system is configured to process the third intermediate image data. The system generally includes a fourth processor. The fourth processor of the system is configured to process the second image data.

Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

Abstract: Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.

Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components.

Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules.

Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules.

Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.