Patents by Inventor Pane-Chane Chao
Pane-Chane Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10529820Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.Type: GrantFiled: July 15, 2015Date of Patent: January 7, 2020Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Kanin Chu, Pane Chane Chao, Carlton T Creamer
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Publication number: 20190043709Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.Type: ApplicationFiled: July 15, 2015Publication date: February 7, 2019Inventors: Kanin Chu, Pane Chane Chao, Carlton T. Creamer
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Patent number: 9136111Abstract: A field effect transistor and method for making such a transistor is provided, the field effect transistor comprising: a gate layer stack comprising a layer of a first metal is disposed proximate to at least one layer of a second metal, wherein the first metal alloys with the second metal to form a shape memory alloy. The shape metal allow may be NiTi, and at the contact plane between the layers, the alloy is formed when the transistor is heated to an elevated temperature.Type: GrantFiled: June 29, 2012Date of Patent: September 15, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Kanin Chu, Pane-Chane Chao, Kirby B. Nichols, Gabriel Cueva
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Patent number: 9117838Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.Type: GrantFiled: April 10, 2013Date of Patent: August 25, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Dong Xu, Xiaoping S. Yang, Wendell Kong, Lee M. Mohnkern, Phillip M. Smith, Pane-chane Chao
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Patent number: 9024326Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.Type: GrantFiled: July 18, 2012Date of Patent: May 5, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Robert Actis, Pane-chane Chao, Robert J. Lender, Jr., Kanin Chu, Bernard J. Schmanski, Sue May Jessup
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Publication number: 20130341644Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.Type: ApplicationFiled: July 18, 2012Publication date: December 26, 2013Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Robert Actis, Pane-chane Chao, Bernard J. Schmanski, Anthony A. Immorlica, Kanin Chu, Robert J. Lender, JR., Dong Xu, Sue May Jessup
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Patent number: 8445941Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.Type: GrantFiled: August 5, 2009Date of Patent: May 21, 2013Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Dong Xu, Xiaoping S. Yang, Wendell Kong, Lee M. Mohnkern, Phillip M. Smith, Pane-chane Chao
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Patent number: 8304332Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: GrantFiled: June 1, 2011Date of Patent: November 6, 2012Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
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Publication number: 20120205726Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: ApplicationFiled: June 1, 2011Publication date: August 16, 2012Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
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Publication number: 20120208359Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: ApplicationFiled: June 1, 2011Publication date: August 16, 2012Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
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Patent number: 8003504Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: GrantFiled: August 31, 2007Date of Patent: August 23, 2011Assignees: BAE Systems Information and Electronic Systems Integration Inc., Biogen IDEC MA Inc.Inventors: Anthony A. Immorlica, Pane-chane Chao, Kanin Chu
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Patent number: 7943286Abstract: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.Type: GrantFiled: March 27, 2008Date of Patent: May 17, 2011Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Dong Xu, Gabriel Cueva, Pane-chane Chao, Wendell Kong
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Publication number: 20100301395Abstract: A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.Type: ApplicationFiled: August 5, 2009Publication date: December 2, 2010Inventors: Dong Xu, Xiaoping Yang, Wendell Kong, Lee M. Mohnkern, Phillip M. Smith, Pane-chane Chao
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Publication number: 20100163936Abstract: A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.Type: ApplicationFiled: August 31, 2007Publication date: July 1, 2010Inventors: Anthony A. Immorlica, Pane-Chane Chao, Kanin Chu
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Publication number: 20080241757Abstract: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.Type: ApplicationFiled: March 27, 2008Publication date: October 2, 2008Inventors: Dong Xu, Gabriel Cueva, Pane-chane Chao, Wendell Kong
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Patent number: 4673960Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.Type: GrantFiled: July 31, 1985Date of Patent: June 16, 1987Assignee: Cornell Research Foundation, Inc.Inventors: Pane-Chane Chao, Walter H. Ku
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Patent number: 4551905Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.Type: GrantFiled: November 9, 1983Date of Patent: November 12, 1985Assignee: Cornell Research Foundation, Inc.Inventors: Pane-Chane Chao, Walter H. Ku
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Patent number: 4536942Abstract: A method of fabricating MESFET devices having a T-shaped gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of dual-angle evaporation gate walls within said resist cavity, the gate walls defining a T-shaped gate cavity; depositing gate electrode material within the gate cavity, removing the resist material, and removing the gate walls from the gate electrode material.Type: GrantFiled: October 5, 1984Date of Patent: August 27, 1985Assignee: Cornell Research Foundation, Inc.Inventors: Pane-Chane Chao, Walter H. Ku