Abstract: The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch SM to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array CA including a binary array of P-bit unit capacitors, a calibration structure Cfraq, and a ground switch Sk. The calibration structure Cfraq includes four unit capacitors and two switches S1 and S2. By controlling the switches S1 and S2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.

Abstract: Disclosed is a three-axis Hall angle sensor with an accuracy of 0.3°. The sensor is mainly designed by means of finite element software and COMSOL Multiphysics. The present specification will be mainly performed in three steps. In the first step, a cross-shape horizontal Hall element for measuring the magnetic field in the vertical direction, that is, the direction z, is studied. The second section mainly studies a three-contact four-Hall vertical element for measuring the magnetic field in the directions x, y. The third part is to design the angle sensor. Compared with the horizontal Hall element, the vertical Hall element has a relatively large offset, therefore, four vertical Hall elements are used to measure the magnetic field in the horizontal direction, and two complementary vertical structures are used to eliminate the error when the magnetic field in the same horizontal direction is measured.