Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.

Abstract: A variety of embodiments may include a voltage controlled oscillator to generate a differential signal on two nodes; and phase detector to compare a phase of the differential signal and a phase of a received signal, the phase detector including a sampling circuit to periodically sample voltage values on the two nodes, and a linear voltage-to-current converter responsive to the voltage values to create a control voltage for the voltage controlled oscillator.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.