Patents by Inventor Pang-Chi Wu
Pang-Chi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961886Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.Type: GrantFiled: November 1, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20230411280Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.Type: ApplicationFiled: August 23, 2023Publication date: December 21, 2023Inventors: Hao Kuang, Tung-Heng Hsieh, Sheng-Hsiung Wang, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu
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Publication number: 20230335469Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.Type: ApplicationFiled: April 15, 2022Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Heng WANG, Pang-Chi WU, Chao-Hsun WANG, Fu-Kai YANG, Mei-Yun WANG
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Publication number: 20230326804Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: ApplicationFiled: June 15, 2023Publication date: October 12, 2023Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Patent number: 11721590Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: GrantFiled: July 12, 2022Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20230049010Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.Type: ApplicationFiled: November 1, 2022Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Heng WANG, Pang-Chi WU, Chao-Hsun WANG, Fu-Kai YANG, Mei-Yun WANG
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Publication number: 20230033570Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh WU, Pang-Chi Wu, Wang-Jung Hsueh, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Yi-Chun Chang, Yuan-Tien Tu
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Patent number: 11527614Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.Type: GrantFiled: May 20, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Heng Wang, Pang-Chi Wu, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20220344215Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: ApplicationFiled: July 12, 2022Publication date: October 27, 2022Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20220293732Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.Type: ApplicationFiled: May 20, 2021Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Heng WANG, Pang-Chi WU, Chao-Hsun WANG, Fu-Kai YANG, Mei-Yun WANG
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Patent number: 11393724Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: GrantFiled: February 8, 2021Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20210166977Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: ApplicationFiled: February 8, 2021Publication date: June 3, 2021Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20210098369Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.Type: ApplicationFiled: July 30, 2020Publication date: April 1, 2021Inventors: Hao Kuang, Tung-Heng Hsieh, Sheng-Hsiung Wang, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu
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Patent number: 10957604Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: GrantFiled: September 11, 2019Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20200135579Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: ApplicationFiled: September 11, 2019Publication date: April 30, 2020Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young