Patents by Inventor Pang-Chun Lin
Pang-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9455159Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: GrantFiled: September 25, 2015Date of Patent: September 27, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
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Patent number: 9362217Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.Type: GrantFiled: May 29, 2014Date of Patent: June 7, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Wei-Ping Wang, Chun-Yuan Li, Shao-tzu Tang, Ying-Chou Tsai
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Patent number: 9318354Abstract: A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer and extending to the switching pads and the first conductive pads; and a semiconductor element disposed on the substrate and electrically connected to the switching pads through a plurality of bonding wires. By electrically connecting the switching pads and the first conductive pads through the conductive layer, the invention dispenses with the conventional short bonding wires so as to prevent the conventional problem of short circuits caused by contact of the short bonding wires with other bonding wires.Type: GrantFiled: June 20, 2013Date of Patent: April 19, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Xie-Ren Cheng
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Publication number: 20160013074Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: ApplicationFiled: September 25, 2015Publication date: January 14, 2016Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
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Patent number: 9177837Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: GrantFiled: March 21, 2014Date of Patent: November 3, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 9171741Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: GrantFiled: August 3, 2012Date of Patent: October 27, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu
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Patent number: 9029203Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.Type: GrantFiled: August 20, 2013Date of Patent: May 12, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Publication number: 20150091150Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.Type: ApplicationFiled: May 29, 2014Publication date: April 2, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pang-Chun Lin, Wei-Ping Wang, Chun-Yuan Li, Shao-tzu Tang, Ying-Chou Tsai
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Patent number: 8981575Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8873244Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.Type: GrantFiled: April 13, 2010Date of Patent: October 28, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Hsiao-Jen Hung, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20140284803Abstract: A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer and extending to the switching pads and the first conductive pads; and a semiconductor element disposed on the substrate and electrically connected to the switching pads through a plurality of bonding wires. By electrically connecting the switching pads and the first conductive pads through the conductive layer, the invention dispenses with the conventional short bonding wires so as to prevent the conventional problem of short circuits caused by contact of the short bonding wires with other bonding wires.Type: ApplicationFiled: June 20, 2013Publication date: September 25, 2014Inventors: Pang-Chun Lin, Xie-Ren Cheng
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Publication number: 20140239475Abstract: A packaging substrate is disclosed, which includes: an encapsulant having opposite first and second surfaces; a plurality of conductive elements embedded in the encapsulant, wherein each of the conductive elements has a first conductive pad exposed from the first surface of the encapsulant and a second conductive pad exposed from the second surface of the encapsulant; and a protection layer formed on the second surface of the encapsulant and the second conductive pads so as to protect the second surface of the encapsulant from being scratched.Type: ApplicationFiled: June 17, 2013Publication date: August 28, 2014Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Publication number: 20140206146Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: ApplicationFiled: March 21, 2014Publication date: July 24, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8716861Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: GrantFiled: February 27, 2013Date of Patent: May 6, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
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Publication number: 20130344661Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.Type: ApplicationFiled: August 20, 2013Publication date: December 26, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Patent number: 8525336Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.Type: GrantFiled: January 12, 2012Date of Patent: September 3, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Publication number: 20130115738Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: ApplicationFiled: August 3, 2012Publication date: May 9, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu
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Publication number: 20130093086Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.Type: ApplicationFiled: January 12, 2012Publication date: April 18, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Patent number: 8421199Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.Type: GrantFiled: April 29, 2010Date of Patent: April 16, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 8390118Abstract: A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.Type: GrantFiled: August 19, 2010Date of Patent: March 5, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Chun-Yuan Li, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke