Abstract: A VD (vertical diffusion) MOSFET device for use in RF power applications has a split gate structure and an additional, dummy gate is provided between the spaced apart gates and, in operation of the device, is electrically coupled to source electrodes provided outside of the gates. The split gate structure reduces gate overlap capacitance and the dummy gate induces depletion in the semiconductor body of the device and reduces the substrate capacitance. The gate overlap capacitance and the substrate capacitance both contribute to the feedback capacitance of the device which has to be as low as possible for high frequency operation. By reducing both of these components, the invention provides advantageous high frequency operation.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: A pressure sensor fabricated onto a substrate using conventional CMOS fabrication processes. The pressure sensor is built on a substrate having a first conductivity type and has defined in it a well of an opposite conductivity type. This well defines a membrane. Resistors are diffused into the well. Source/drain regions are provided for leadouts for the resistors. An n-cap is provided for the resistors. Metalization contacts may be provided to connect the membrane to a positive bias during a membrane etching process. A cavity is provided on the underside of the substrate through which pressure is applied to the membrane. Signal conditioning circuitry, such as an operational amplifier, may also be fabricated on the same substrate preferably using the same IC processes.

Abstract: An apparatus for sensing an applied force comprising a deflectable bridge, formed in a substrate and spanning a recessed area. The deflectable bridge also has a sensing element. The force is applied to the bridge and in response thereto, an output characteristic of the sensing element changes in proportion to the magnitude of the applied force. The apparatus can further comprise a sensing bump in contact with the bridge, wherein the force is applied to the bridge through the sensing bump.

Abstract: The use of a deposition process involving a plasma struck in a gas including tetraethoxysilane and a source of oxygen yields, at low temperatures, conformal coatings of silicon dioxide. This process has significant implications for semiconductor device fabrication involving the deposition of a dielectric over a metallic non-planar structure.

Abstract: Integrated circuits employing titanium nitride are significantly improved by using a specific method for formation of the titanium nitride in the device fabrication. In particular, a plasma such as one formed in an electron cyclotron resonance apparatus is employed to dissociate a source of nitrogen and a source of hydrogen and the dissociation products are combined at the integrated circuit deposition substrate with titanium tetrachloride. The resulting deposition is essentially devoid of chlorine and has advantageous step-coverage properties.

Abstract: A method of forming silicon dioxide layers by bias ECR is described. The layers are formed by reacting oxygen with TEOS or TMCTS. High-quality, void-free layerc can be formed over conductor patterns having high-aspect-ratio intermetallic spacings.

Abstract: Disclosed is a method for forming a silicon dioxide layer on a substrate by radio-frequency deposition from a plasma comprising oxygen, argon, and tetraethyl orthosilicate (TEOS) or tetramethyl cyclotetrasiloxane (TMCTS). A negative bias is imparted to the substrate. The resulting ion bombardment induces surface migration. Because TEOS and TMCTS have a relatively high mean free path for surface migration, the filling of soft spots and key holes is promoted.

Abstract: In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors.

Abstract: By adjusting the AC field conditions, i.e., by grounding the environment of a substrate being etched with a chlorine-containing plasma, a significant increase in etch selectivity is achieved. By applying a similar AC field adjustment to the reaction chamber surfaces, excellent etch uniformity is achieved in conjunction with excellent selectivity.