Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 kgf, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70), a plurality of pads (100) centrally disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) adhered to the second surface (84) of the substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the openings (86) to adhere the chip (50) to the substrate (70) and surrounding the wire bonding (80), is disclosed.

Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip.At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate.

Abstract: An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.