Abstract: Provided is a semiconductor device which may include: a plurality of gate structures arranged at a predetermined gate pitch in a 1st direction and extended in a 2nd direction; and a plurality of metal lines arranged at two or more different metal pitches in the 1st direction and extended in the 2nd direction at a same level in a 3rd direction.

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

Abstract: An integrated circuit device includes a wimpy transistor stack on a substrate, wherein the wimpy transistor stack comprises: an upper transistor comprising: a plurality of upper channel regions stacked in a vertical direction; and an upper source/drain region that contacts at least one of the plurality of upper channel regions; a lower transistor that is between the substrate and the upper transistor and comprises: a plurality of lower channel regions stacked in the vertical direction; and a lower source/drain region that contacts at least one of the plurality of lower channel regions; and a source/drain isolation layer separating the upper source/drain region from the lower source/drain region, wherein the source/drain isolation layer contacts a lowermost one of the plurality of upper channel regions and/or an uppermost one of the plurality of lower channel regions.

Abstract: An integrated circuit device includes a wimpy transistor stack and a reference transistor stack on a substrate. The wimpy transistor stack may include a first intergate insulator that is thicker than a second intergate insulator of the reference transistor stack. Due to the thicker first intergate insulator, a number of first upper channel regions of the wimpy transistor stack may be less than a number of second upper channel regions of reference transistor stack, and/or a number of first lower channel regions of the wimpy transistor stack may be less than a number of second lower channel regions of the reference transistor stack.

Abstract: Provided is a semiconductor device based on a cell architecture which includes: a 1st semiconductor cell; and a 2nd semiconductor cell which is connected to the 1st semiconductor cell in a 1st direction such that an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell, wherein the 2nd semiconductor cell is in a form in which the 1st semiconductor cell is turned upside down.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.

Abstract: Integrated circuit devices may include an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode. The lower gate electrode may be electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact may protrude beyond a side surface of the lower gate electrode.

Abstract: Provided is a semiconductor device including a 1st frontside metal line at a front side of the semiconductor device; and a 1st backside metal line at a back side of the semiconductor device, wherein the 1st backside metal line is connected to the 1st frontside metal line.

Abstract: Provided is a semiconductor cell architecture which includes a plurality of cells, a plurality of backside power rails, and a plurality of metal lines, wherein the backside power rails are extended in a cell-length direction, and at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view.

Abstract: Provided is a semiconductor device in which a large-CPP area includes a 1st source/drain structure; a 1st frontside contact structure, at a front side of the semiconductor device, connected to the 1st source/drain structure; a 1st via structure, at a lateral side of the 1st source/drain structure, connected to the 1st frontside contact structure; a 2nd via structure on the 1st frontside via structure; a 1st frontside metal line, at the front side of the semiconductor device, connected to the 2nd via structure; and a 1st backside metal line, at a back side of the semiconductor device, connected to the 1st via structure.

Abstract: Provided is a semiconductor device which includes: a backside contact plug, formed at a back side of the semiconductor device, below a source/drain region connected to the backside contact plug, wherein the backside contact plug includes a 1st portion which is not vertically overlapped by the circuit element.

Abstract: Provided is a semiconductor device including a 3DSFET device which includes: a 1st source/drain region; a 2nd source/drain region, above the 1st source/drain region, having a smaller width than the 1st source/drain region, the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure; a 1st contact plug on the 1st source/drain region; a 2nd contact plug on the 2nd source/drain region; and a 2nd isolation structure, between the 1st contact plug and the 2nd contact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation structure.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: A cell architecture including at least one semiconductor device cell is provided.

Abstract: A semiconductor device includes first standard cells arranged in a first row on a substrate and respectively including a first base active region, second standard cells arranged in a second row adjacent to the first row and respectively including a second base active region, a power line extending in a first direction along a boundary between the first and second standard cells, and a device isolation layer on side surfaces of the first and second base active regions, wherein, in a plan view, the first standard cells and the second standard cells have a same cell height, the first base active region of each of the first standard cells includes a first active line having a first conductivity-type and a second active line having a second conductivity-type, the second base active region of each of the second standard cells includes a third active line having the first conductivity-type and a fourth active line having the second conductivity-type, the first active lines of the first standard cells arranged in the

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

Abstract: Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region

Abstract: A cell including individual source regions includes active regions extending in a first direction and being spaced apart from each other in a second direction different from the first direction, gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction, first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions, metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction, second contacts connecting the gate lines to the metal lines, and vias connecting the first contacts to the metal lines.

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate electrode intersecting the active region and extending in a second direction, perpendicular to the first direction, a contact structure disposed on the active region on one side of the gate electrode and extending in the second direction, and a first via disposed on the contact structure to be connected to the contact structure and has a shape in which a length in the second direction is greater than a length in the first direction. A plurality of first metal interconnections are provided, which extend in the first direction on the first via, and are connected to the first via. A second via is provided, which is disposed on the plurality of first metal interconnections to be connected to the plurality of first metal interconnections and has a shape in which a length in the second direction is greater than a length in the first direction.

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.