Abstract: A semiconductor device includes first standard cells arranged in a first row on a substrate and respectively including a first base active region, second standard cells arranged in a second row adjacent to the first row and respectively including a second base active region, a power line extending in a first direction along a boundary between the first and second standard cells, and a device isolation layer on side surfaces of the first and second base active regions, wherein, in a plan view, the first standard cells and the second standard cells have a same cell height, the first base active region of each of the first standard cells includes a first active line having a first conductivity-type and a second active line having a second conductivity-type, the second base active region of each of the second standard cells includes a third active line having the first conductivity-type and a fourth active line having the second conductivity-type, the first active lines of the first standard cells arranged in the

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

Abstract: Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region

Abstract: A cell including individual source regions includes active regions extending in a first direction and being spaced apart from each other in a second direction different from the first direction, gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction, first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions, metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction, second contacts connecting the gate lines to the metal lines, and vias connecting the first contacts to the metal lines.

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate electrode intersecting the active region and extending in a second direction, perpendicular to the first direction, a contact structure disposed on the active region on one side of the gate electrode and extending in the second direction, and a first via disposed on the contact structure to be connected to the contact structure and has a shape in which a length in the second direction is greater than a length in the first direction. A plurality of first metal interconnections are provided, which extend in the first direction on the first via, and are connected to the first via. A second via is provided, which is disposed on the plurality of first metal interconnections to be connected to the plurality of first metal interconnections and has a shape in which a length in the second direction is greater than a length in the first direction.

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.