Abstract: A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.

Abstract: Methods, devices, and systems are provided for synchronizing a source device with a sink device. In some examples, the source device plays first audio using, e.g., an electro-acoustic transducer. The source device transmits a stream of packets to the sink device to be used by the sink device for playing second audio, where the playing of the second audio is to be synchronized within a predefined tolerance with the playing of the first audio. In response to determining there is a delay in average packet arrival times of the stream of packets at the sink device, the source device adjusts the playing of the first audio to maintain synchronization with the playing of the second audio within the predefined tolerance.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

Abstract: A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

Abstract: Systems and methods are disclosed herein for computer-aided method for developing, customizing, and deploying a platform where people can provide service to other users based on a trust among multiple individuals. This is especially useful among ecommerce applications where users can initiate and complete an ecommerce transaction with an individual not directly trusted.

Abstract: A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.

Abstract: A circuit includes a bit line, a pass gate coupled between the bit line and a power node having a first power voltage level, and a driver coupled between the bit line and a reference node having a reference voltage level. The pass gate couples the bit line to the power node when the first signal has the reference voltage level and decouples the bit line from the power node when the first signal has the first power voltage level. The driver receives a second signal based on a control signal, couples the bit line to the reference node when the second signal has a second power voltage level below the first power voltage level, and decouples the bit line from the reference node when the second signal has the reference voltage level. An input circuit generates the first signal independent of the control signal.

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

Abstract: A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

Abstract: A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.

Abstract: Technology described in this document can be embodied in a method for facilitating automatic connection to a network. The method includes receiving, at a first device that is authenticated to the network, an identifier of a second device, and retrieving, by the first device based on the identifier, a public key for the second device. The data encrypted using the public key is decryptable using a private key of the second device. The method also includes encrypting, using the public key for the second device, credential information usable by the second device for authenticating to the network, and transmitting, to the second device, the encrypted credential information.

Abstract: A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

Abstract: A circuit includes a bit line, a pass gate coupled between the bit line and a power node having a first power voltage level, and a driver coupled between the bit line and a reference node having a reference voltage level. The pass gate couples the bit line to the power node when the first signal has the reference voltage level and decouples the bit line from the power node when the first signal has the first power voltage level. The driver receives a second signal based on a control signal, couples the bit line to the reference node when the second signal has a second power voltage level below the first power voltage level, and decouples the bit line from the reference node when the second signal has the reference voltage level. An input circuit generates the first signal independent of the control signal.

Abstract: A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.

Abstract: A circuit includes a bit line, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate couples the bit line to the power node responsive to a first signal, and the driver couples the bit line to the reference node responsive to a second signal. The first signal is based on the first power voltage level, and the second signal is based on a second power voltage level between the reference voltage level and the first power voltage level.

Abstract: A method is provided for managing a number of active wireless data streams in a device. An operating band of the device is detected, wherein the device is capable of simultaneously supporting Wi-Fi and Bluetooth communications by time sharing the operating band between the Wi-Fi and Bluetooth communications. A request is detected for simultaneously operating in at least two of a Wi-Fi communication mode, a Bluetooth source communication mode, or a Bluetooth sink communication mode. In response to detecting the request, only two of the Wi-Fi communication mode, the Bluetooth source communication mode, or the Bluetooth sink communication mode are selected.

Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.