Patents by Inventor Pankaj BONGALE

Pankaj BONGALE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for optimal trim calibrations in integrated circuits
    Patent number: 10606723
    Abstract: A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pankaj Bongale, Partha Ghosh, Rubin Ajit Parekhji
  • SYSTEMS AND METHODS FOR OPTIMAL TRIM CALIBRATIONS IN INTEGRATED CIRCUITS
    Publication number: 20170177456
    Abstract: A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Pankaj BONGALE, Partha GHOSH, Rubin Ajit PAREKHJI