Abstract: A ball detection and tracking system including one or more visual sensors and a detection and tracking agent that ranks a plurality of blob detection algorithms based on a detection metric and uses a selected base detection algorithm to identify one or more candidate blobs. Based on this, the agent is able to generate a track for the candidate blobs and assign one or more subsequent candidate blobs to a best ranked one of the tracks if the assignment satisfies a cost threshold.

Abstract: Systems, methods and computer programs are disclosed for providing an indication of a decoding problem in a wireless system. A problem is detected in decoding uplink physical control channels for a Dedicated Physical Control Channel (DPCCH) or an Enhanced Dedicated Physical Control Channel (E-DPCCH). A modified Up Link (UL) Dedicated Channel (DCH) frame having a spare field modified to indicate a Transport Format Combination Indicator (TFCI) decode failure is sent. In response to receiving the modified UL DCH frame, an Up Link (UL) Outer-Loop Power Control (OLPC) is controlled to keep a signal-to-interference ratio (SIR) of the UL DPCCH within a predetermined range.

Abstract: A ball detection and tracking system including one or more visual sensors and a detection and tracking agent that ranks a plurality of blob detection algorithms based on a detection metric and uses a selected base detection algorithm to identify one or more candidate blobs. Based on this, the agent is able to generate a track for the candidate blobs and assign one or more subsequent candidate blobs to a best ranked one of the tracks if the assignment satisfies a cost threshold.

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract: Various embodiments of methods and systems for deep coalescing memory management (“DCMM”) in a portable computing device (“PCD”) are disclosed. Because multiple active multimedia (“MM”) clients running on the PCD may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“DDR”) memory component, DCMM solutions triage the requests into dedicated deep coalescing (“DC”) cache buffers, sequentially ordering the requests and/or the DC buffers based on associated addresses for the data in the DDR, to optimize read and write transactions from and to the DDR memory component in blocks of contiguous data addresses.

Abstract: Ephemeral data stored in a cache is read when needed but is not written to system memory so as to save power and bandwidth. In an embodiment, a no-writeback bit associated with the ephemeral data is set in response to a read-no-writeback instruction. Data in a cache line for which its no-writeback bit has been set is not written back into system memory. Accordingly, when evicting cache lines, if a cache line has a no-writeback bit set, then the data in that cache line is discarded without being written back to system memory.

Abstract: A video processor is described, which is useful for implementing a forward transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 forward transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Abstract: A video processor is described, which is useful for implementing a Hadamard transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 Hadamard transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Abstract: A video processor is described, which is useful for implementing a quantization process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a quantizer, which incorporates the quantization lookup tables associated with the H.264 standard in its associated hardware, makes necessary high-level quantization decisions. In response to receiving another SIMD instruction, the quantizer uses those high-level quantization decisions to retrieve specific values from the quantization lookup tables.

Abstract: A video encoding method and a video encoder are described for processing frames in a group of pictures (GOP). A difference between a bit budget of a selected frame in the GOP and an estimated number of bits consumed by the selected frame is determined. Quantization parameter (Qp) values assigned to coefficients of macroblocks (MBs) in the selected frame are adjusted if the difference does not fall within a tolerance. The Qp values may be filtered. A bit budget to the GOP may be assigned or adjusted based on a target bitrate. A bit budget may be assigned to each unprocessed frame in the GOP. Spatial activity may be calculated for each MB in the selected frame, and a bit budget and quantization may be assigned for each MB in the selected frame based on the spatial activity.

Abstract: Several different approaches to performing the modulus operation are presented. In one, a method of performing the modulus operation upon a dividend and a divisor within a limited range is discussed. The method involves storing a reference value, receiving a dividend value, and calculating a number of derived inputs. Each of the derived inputs corresponds to the dividend value minus the reference value, and is then further modified by a multiple of the divisor. Using the divisor to select between these derived inputs provides the answer.

Abstract: A bitstream generator is described, for placing variable length coding (VLC) data into a fixed width data stream. The bitstream generator includes an input for receiving VLC data; the VLC data may be separated into a value component, and a length component. The bitstream generator also includes an output buffer, a memory module, for storing the VLC data before sending. The bitstream generator also incorporates a backup buffer, which is used to store any overflow data which does not fit in the output buffer. A comparator is used, to determine how much of the VLC data will fit in the output buffer. Any portion of the VLC data which does not fit in the output buffer is stored in the backup buffer.