Patents by Inventor Pankaj Gupta
Pankaj Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250136720Abstract: This invention relates to binding molecules that bind specifically to CD137 and FAP and their use in medicine, pharmaceutical compositions containing the same, and methods of using the same as agents for treatment and/or prevention of cancer.Type: ApplicationFiled: October 2, 2024Publication date: May 1, 2025Inventors: Eric BORGES, Pankaj GUPTA, Daniel Christopher ROWE, Justin M. SCHEER, Abdallah SOUABNI, Inigo TIRAPU, Joseph Ronald TUMANG
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Patent number: 12275798Abstract: The present invention relates to novel tri-specific binding molecules. The invention also relates to nucleic acids encoding such binding molecules; to methods for preparing such binding molecules; to host cells expressing or capable of expressing such binding molecules; to compositions comprising such binding molecules; and to uses of such binding molecules or such compositions, in particular for therapeutic purposes in the field of cancer diseases.Type: GrantFiled: June 15, 2022Date of Patent: April 15, 2025Assignee: Boehringer Ingelheim International GmbHInventors: Paul Adam, Stephen R. Comeau, Philip Nicholas Gorman, Pankaj Gupta, Priyanka Gupta, Karl-Heinz Heider, Srinath Kasturirangan, Renate Konopitzky, Klaus-Peter Kuenkele, Sandeep Kumar, Taneisha Ann-Tanara Mack, Elinborg Katrin Ostermann, Abdulsalam Shaaban, David Weismann, Andreas Wernitznig, David S. Young
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Publication number: 20250088449Abstract: Some embodiments provide a method for a data message processing device that includes multiple network interfaces associated with at least two different non-uniform memory access (NUMA) nodes. The method receives a data message at a first network interface associated with a particular one of the NUMA nodes. Based on processing of the data message, the method identifies multiple output options for the data message. Each of the output options has an equal forwarding cost and each output option is associated with a respective one of the NUMA nodes. The method selects an output option for the data message that is associated with the particular NUMA node to avoid cross-NUMA node processing of the data message.Type: ApplicationFiled: September 8, 2023Publication date: March 13, 2025Inventors: Xinhua Hong, Jochen Behrens, Yu Ying, Pankaj Gupta
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Publication number: 20250036437Abstract: Some embodiments provide a method for configuring a first Pod in a container cluster to perform layer 7 (L7) services for a logical router. At a second Pod that performs logical forwarding operations for the logical router, the method receives configuration data for the logical router from a network management system that defines a logical network for which the logical router routes data messages and performs L7 services. The method provides a set of Pod definition data to a cluster controller to create the first Pod. After creation of the first Pod, the method provides to the first Pod (i) networking information to enable a connection between the first and second Pods and (ii) configuration data defining the L7 services for the first Pod to perform the L7 services on data traffic sent from the second Pod to the first Pod.Type: ApplicationFiled: July 24, 2023Publication date: January 30, 2025Applicant: VMware, Inc.Inventors: Yu Ying, Pankaj Gupta, Kai-Wei Fan, Stephen Tan, Sreeram Kumar Ravinoothala, Yong Wang
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Publication number: 20250039088Abstract: Some embodiments provide a method for implementing a logical router of a logical network at a first Pod executing on a first node of a Kubernetes cluster to implement data message forwarding for the logical router. The method receives a data message for processing by the logical router. The method determines that the data message requires layer 7 (L7) service processing at the logical router. The method selects a second Pod from multiple Pods that perform L7 service for the logical router. Each of the Pods executes on a different node of the cluster. The method forwards the data message to the second Pod via a layer 2 (L2) construct that connects the first and second Pods.Type: ApplicationFiled: July 24, 2023Publication date: January 30, 2025Inventors: Yu Ying, Yong Wang, Pankaj Gupta, Sreeram Kumar Ravinoothala
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Publication number: 20250020771Abstract: Devices, e.g., hardware accelerators, and systems are operable to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.Type: ApplicationFiled: October 2, 2024Publication date: January 16, 2025Inventors: Pankaj Gupta, Karthik Ramasubramanian
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Patent number: 12182682Abstract: Provided is a ticketing system adapted to retrieve a recommendation from a knowledge database in response to a received query, the ticketing system including a processor adapted to perform semantic similarity learning in textual description pairs by calculating similarity scores for similarities between the received query and tickets stored in the knowledge database of the ticketing system, wherein each textual description pair includes a textual description of the received query and a textual description of a ticket of a plurality of tickets stored in the knowledge database of the ticketing system, wherein the ticket having the maximum similarity score is identified and a solution of the identified ticket is output as the retrieved recommendation for the received query by the ticketing system.Type: GrantFiled: January 23, 2018Date of Patent: December 31, 2024Assignee: Siemens AktiengesellschaftInventors: Bernt Andrassy, Pankaj Gupta
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Patent number: 12173083Abstract: The present invention relates to novel DLL3/CD3 binding proteins. The invention also relates to nucleic acids encoding such proteins; to methods for preparing such proteins; to host cells expressing or capable of expressing such proteins; to compositions comprising such proteins; and to uses of such proteins or such compositions, in particular for therapeutic purposes in the field of cancer diseases.Type: GrantFiled: March 4, 2022Date of Patent: December 24, 2024Assignee: Boehringer Ingelheim International GmbHInventors: Susanne Hipp, Paul Adam, Michael Dziegelewski, Rajkumar Ganesan, Philip Nicholas Gorman, Priyanka Gupta, Justin Scheer, Vladimir H. Voynov, Pankaj Gupta
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Publication number: 20240415628Abstract: An embolic protection device with a flexible fiber-based filter element is described associated with an integrated guide structure. The integrated guide structure comprises a corewire within a hypotube having an uncut proximal section and a distal section having laser cuts through the hypotube wall. A corewire extends through the hypotube with a low friction channel, which can have a friction reducing coil between the corewire and at least a portion of the hypotube. A torque coupler restricts rotation of the corewire while allowing at least some sliding of the corewire within the hypotube that provides for actuating the filter element and for curving the laser cut hypotube. Torque coupler designs provide connection to the laser cut hypotube. The fiber bundle has an initial undeployed configuration with the fibers aligned and a deployed configuration with the fibers bent.Type: ApplicationFiled: June 13, 2023Publication date: December 19, 2024Inventors: John Wainwright, Joseph Marrocco, Charles M T Gordon, Charles L. Anderson, Julia Holmstrom, Christian G. Monroe, Jack B. Sattell, Brendan Gonzales, Pankaj Gupta, Englong Tan
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Patent number: 12146000Abstract: This invention relates to binding molecules that bind specifically to CD137 and FAP and their use in medicine, pharmaceutical compositions containing the same, and methods of using the same as agents for treatment and/or prevention of cancer.Type: GrantFiled: May 18, 2021Date of Patent: November 19, 2024Assignee: Boehringer Ingelheim International GmbHInventors: Eric Borges, Pankaj Gupta, Daniel Christopher Rowe, Justin M. Scheer, Abdallah Souabni, Inigo Tirapu, Joseph Ronald Tumang
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Patent number: 12141544Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.Type: GrantFiled: June 15, 2023Date of Patent: November 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Indu Prathapan, Puneet Sabbarwal, Pankaj Gupta
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Patent number: 12130378Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.Type: GrantFiled: January 11, 2022Date of Patent: October 29, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pankaj Gupta, Karthik Ramasubramanian
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Publication number: 20240356496Abstract: An example apparatus includes: memory having a terminal, the memory to store machine-readable instructions and adjacent channel leakage data; and programmable circuitry having a terminal coupled to the terminal of the memory, the programmable circuitry to execute the machine-readable instructions to: determine a range of out-of-band frequencies responsive to adjacent channel leakage ratio data; generate weight values responsive to electromagnetic emissions within the range of out-of-band frequencies of a first signal; modify a pre-distortion function responsive to the weight values; and apply the modified pre-distortion function to generate a second signal, the second signal to exhibit fewer emissions in the range of out-of-band frequencies than the first signal during transmission.Type: ApplicationFiled: March 25, 2024Publication date: October 24, 2024Inventors: Pankaj Gupta, Jawaharlal Tangudu, Manchi Sankalkar Ajay, Mathews John, Jaiganesh Balakrishnan, Neeraj Kumar Sharma
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Publication number: 20240345805Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Pankaj GUPTA, Karthik SUBBURAJ, Sujaata RAMALINGAM, Karthik RAMASUBRAMANIAN, Indu PRATHAPAN
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Patent number: 12057854Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.Type: GrantFiled: February 28, 2022Date of Patent: August 6, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pankaj Gupta, Ajai Paulose, Sreenath Narayanan Potty, Divyansh Jain, Jaiganesh Balakrishnan, Jawaharlal Tangudu, Aswath VS, Girish Nadiger, Ankur Jain
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Patent number: 12045582Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.Type: GrantFiled: June 18, 2021Date of Patent: July 23, 2024Assignee: Texas Instruments IncorporatedInventors: Pankaj Gupta, Karthik Subburaj, Sujaata Ramalingam, Karthik Ramasubramanian, Indu Prathapan
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Publication number: 20240184846Abstract: An example apparatus includes: programmable circuitry to receive an input signal, a digital pre-distorter (DPD) output signal, and a power amplifier (PA) feedback signal; populate a partial matrix with a threshold number of rows of equation terms; compute a respective observation terms for each row in the threshold number of rows; reduce the partial matrix into a Hermitian matrix and reduce the observation terms into a vector; accumulate the Hermitian matrix and the vector onto the memory; regularize, after a determination that a threshold number of Hermitian matrices have been accumulated, the memory to form an output matrix; and pre-distort the input signal using the output matrix.Type: ApplicationFiled: March 31, 2023Publication date: June 6, 2024Inventors: Mathews John, Pankaj Gupta, Jawaharlal Tangudu, Pankaj Gaur, Shikhar Chouhan, Manchi Sankalkar Ajay
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Publication number: 20240183939Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.Type: ApplicationFiled: January 23, 2024Publication date: June 6, 2024Inventors: Sujaata Ramalingam, Karthik Subburaj, Pankaj Gupta, Anil Varghese Mani, Karthik Ramasubramanian, Indu Prathapan
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Patent number: 11999800Abstract: This invention relates to binding molecules that bind specifically to CD137 and FAP and their use in medicine, pharmaceutical compositions containing the same, and methods of using the same as agents for treatment and/or prevention of cancer.Type: GrantFiled: May 18, 2021Date of Patent: June 4, 2024Assignee: Boehringer Ingelheim International GmbHInventors: Eric Borges, Pankaj Gupta, Daniel Christopher Rowe, Justin M. Scheer, Abdallah Souabni, Inigo Tirapu, Joseph Ronald Tumang
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Publication number: 20240143282Abstract: In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Inventors: Mathews John, Jawaharlal Tangudu, Pankaj Gaur, Divyansh Jain, Pankaj Gupta