Patents by Inventor Pankaj Kalra
Pankaj Kalra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9318533Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.Type: GrantFiled: August 18, 2014Date of Patent: April 19, 2016Assignee: SANDISK 3D LLCInventors: Pankaj Kalra, Chandrasekhar Gorla, Masaaki Higashitani
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Patent number: 8988936Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: GrantFiled: October 4, 2014Date of Patent: March 24, 2015Assignee: SanDisk 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20150023113Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: ApplicationFiled: October 4, 2014Publication date: January 22, 2015Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20150023115Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: ApplicationFiled: October 4, 2014Publication date: January 22, 2015Inventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Patent number: 8934295Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: GrantFiled: October 4, 2014Date of Patent: January 13, 2015Assignee: Sandisk 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20140353573Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.Type: ApplicationFiled: August 18, 2014Publication date: December 4, 2014Inventors: Pankaj Kalra, Chandrasekhar Gorla, Masaaki Higashitani
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Patent number: 8897064Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: GrantFiled: April 16, 2014Date of Patent: November 25, 2014Assignee: Sandisk 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorta
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Patent number: 8885400Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: GrantFiled: February 21, 2013Date of Patent: November 11, 2014Assignee: SanDisk 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20140233327Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: ApplicationFiled: April 16, 2014Publication date: August 21, 2014Applicant: SANDISK 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20140233329Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: SANDISK 3D LLCInventors: Yingchang Chen, Pankaj Kalra, Chandrasekhar Gorla
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Publication number: 20130332227Abstract: A method of, system for, and article of manufacture for organizing and managing a household unit using a communications network. The method may include acquiring information from plural members of a household; acquiring planning information for a household-oriented goal(s); and sharing, with a third party via the network, data and content associated with the household-oriented goal(s) in order to solicit targeted quotes from the third party to accomplish the household-oriented goal(s).Type: ApplicationFiled: June 7, 2013Publication date: December 12, 2013Inventors: Khannan Sankaran, Ashish Sanan, Shalesh Jawa, Pankaj Kalra
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Patent number: 8547725Abstract: A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.Type: GrantFiled: February 10, 2010Date of Patent: October 1, 2013Assignee: SanDisk 3D LLCInventors: Tanmay Kumar, Roy Scheuerlein, Pankaj Kalra, Jingyan Zhang
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Patent number: 8436447Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.Type: GrantFiled: April 23, 2010Date of Patent: May 7, 2013Assignee: SanDisk 3D LLCInventors: Pankaj Kalra, Raghuveer S. Makala
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Publication number: 20110260290Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.Type: ApplicationFiled: April 23, 2010Publication date: October 27, 2011Inventors: Pankaj Kalra, Raghuveer S. Makala
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Publication number: 20100142256Abstract: A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Inventors: Tanmay KUMAR, Roy E. Scheuerlein, Pankaj Kalra, Jingyan Zhang