Patents by Inventor Pankaj Kansal
Pankaj Kansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230403237Abstract: According to examples, a system for aligning a plurality of variously encoded content streams is described. The system may include a processor and a memory storing instructions. The processor, when executing the instructions, may cause the system to receive a request to transmit one or more packets of a message over a network, upon receive the request, designate a message sequence number (MSN) for the message, and upon receive the request, designate a packet sequence number (PSN) for one or more packets of the message.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: Meta Platforms, Inc.Inventors: Arvind SRINIVASAN, Nicolaas Johannes Viljoen, Pankaj Kansal, Ashay Narsale
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Publication number: 20230385138Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: Pankaj Kansal, Arvind Srinivasan, Harikrishna Madadi Reddy, Naader Hasani
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Publication number: 20230370203Abstract: According to examples, a selective acknowledgement framework may be implemented within a communication system for efficient communication of acknowledgement packets. A plurality of data packets generated from a message may be transmitted as a segment of data packets to a receiver which generates an acknowledgement packet for the segment of data packets. A compact format of acknowledgement (ACK) or negative acknowledgement (NACK) for the segment of data packets may be implemented in the acknowledgement packet via bits of a selective acknowledgement bit vector. Based on the other values also conveyed in the acknowledgement packet, the transmitter may identify those data packets that were properly received and the data packets that need to be re-transmitted.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Meta Platforms, Inc.Inventors: Arvind SRINIVASAN, Zeeshan Altaf LOKHANDWALA, Pankaj KANSAL, Nicolaas Johannes VILJOEN
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Patent number: 11762560Abstract: A system including an array of processing elements, a plurality of periphery crossbars and a plurality of storage components is described. The array of processing elements is interconnected in a grid via a network on an integrated circuit. The periphery crossbars are connected to a plurality of edges of the array of processing elements. The storage components are connected to the periphery crossbars.Type: GrantFiled: December 6, 2021Date of Patent: September 19, 2023Assignee: Meta Platforms, Inc.Inventors: Linda Cheng, Olivia Wu, Abdulkadir Utku Diril, Pankaj Kansal
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Publication number: 20230251903Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Anup Ramesh Kadkol, Aravind Kalaiah, Pankaj Kansal
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Publication number: 20230176736Abstract: A system including an array of processing elements, a plurality of periphery crossbars and a plurality of storage components is described. The array of processing elements is interconnected in a grid via a network on an integrated circuit. The periphery crossbars are connected to a plurality of edges of the array of processing elements. The storage components are connected to the periphery crossbars.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Linda Cheng, Olivia Wu, Abdulkadir Utku Diril, Pankaj Kansal
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Patent number: 11663043Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.Type: GrantFiled: December 2, 2019Date of Patent: May 30, 2023Assignee: Meta Platforms, Inc.Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Anup Ramesh Kadkol, Aravind Kalaiah, Pankaj Kansal
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Patent number: 11537301Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.Type: GrantFiled: May 4, 2021Date of Patent: December 27, 2022Assignee: Meta Platforms, Inc.Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Patent number: 11531619Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.Type: GrantFiled: December 17, 2019Date of Patent: December 20, 2022Assignee: Meta Platforms, Inc.Inventors: Olivia Wu, Abdulkadir Utku Diril, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Publication number: 20210326051Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.Type: ApplicationFiled: May 4, 2021Publication date: October 21, 2021Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Patent number: 11054998Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.Type: GrantFiled: December 12, 2019Date of Patent: July 6, 2021Assignee: Facebook, Inc.Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Publication number: 20210181957Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Publication number: 20210182196Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. Each request processing unit includes a plurality of decomposition units and a crossbar switch, the crossbar switch communicatively connecting each of the plurality of decomposition units to each of the plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access the plurality of memory units using a dynamically programmable distribution scheme.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Olivia Wu, Abdulkadir Utku Diril, Krishnakumar Narayanan Nair, Aravind Kalaiah, Anup Ramesh Kadkol, Pankaj Kansal
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Publication number: 20210165691Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Abdulkadir Utku Diril, Olivia Wu, Krishnakumar Narayanan Nair, Anup Ramesh Kadkol, Aravind Kalaiah, Pankaj Kansal