Patents by Inventor Pankaj P. Chauhan

Pankaj P. Chauhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10515168
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 24, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
  • Patent number: 9817929
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 14, 2017
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Sameer Kapoor, Saurabh Jain, Kunal Bindal, Bryan D. Bowyer, Andres R. Takach, Peter P. Gutberlet, Gagandeep Singh, Maheshinder Goyal
  • Patent number: 8122401
    Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, the transformation identifies a word-level functionality of the at least some of the finite portions by converting bit-level functionality into word-level functionality.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Deepak Goyal, Anmol Mathur
  • Patent number: 8117571
    Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, an abstraction is performed on the netlist.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 14, 2012
    Assignee: Calypto Design Systems, Inc.
    Inventors: Pankaj P. Chauhan, Deepak Goyal, Anmol Mathur