Patents by Inventor Pankaj Raghuvanshi

Pankaj Raghuvanshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10649783
    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.
    Type: Grant
    Filed: April 30, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Patent number: 9690591
    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, processor logic delays the processing of a first instruction for a threshold amount of time if the first instruction within an instruction queue is fusible with a second instruction.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Publication number: 20170003965
    Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
    Type: Application
    Filed: April 30, 2016
    Publication date: January 5, 2017
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Publication number: 20160378487
    Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
    Type: Application
    Filed: April 30, 2016
    Publication date: December 29, 2016
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Patent number: 9494997
    Abstract: In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: November 15, 2016
    Assignee: Apple Inc.
    Inventors: Kulin N. Kothari, Pradeep Kanapathipillai, Chetana N. Keltcher, Pankaj Raghuvanshi
  • Publication number: 20160246600
    Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
    Type: Application
    Filed: April 30, 2016
    Publication date: August 25, 2016
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Publication number: 20150362978
    Abstract: In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventors: Kulin N. Kothari, Pradeep Kanapathipillai, Chetana N. Keltcher, Pankaj Raghuvanshi
  • Publication number: 20150033045
    Abstract: An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: Apple Inc.
    Inventors: Pankaj Raghuvanshi, Rohit Kumar, Suresh Periyacheri
  • Patent number: 8516577
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Michael S. Bair, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover
  • Publication number: 20120072984
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Inventors: MICHAEL S. BAIR, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover
  • Publication number: 20100115248
    Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi