Patents by Inventor Pankaj Rohilla

Pankaj Rohilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low consumption flip-flop circuit with data retention and method thereof
    Patent number: 8570085
    Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 29, 2013
    Assignees: STMicroelectronics S.r.l., STMicroelectronics International NV
    Inventors: Andrea Mario Veggetti, Abhishek Jain, Pankaj Rohilla
  • Low consumption flip-flop circuit with data retention and method thereof
    Patent number: 8330518
    Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: December 11, 2012
    Assignees: STMicroelectronics S.r.l., STMicroelectronics PVT Ltd
    Inventors: Andrea Mario Veggetti, Abhishek Jain, Pankaj Rohilla
  • LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF
    Publication number: 20110176653
    Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 21, 2011
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS PVT LTD
    Inventors: Andrea Mario Veggetti, Abhishek Jain, Pankaj Rohilla
  • Base cell for engineering change order (ECO) implementation
    Patent number: 7965107
    Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 21, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Ciccarelli, Lorenzo Cali, Massimiliano Innocenti, Claudio Mucci, Valentina Nardone, Matteo Pizzotti, Pankaj Rohilla
  • BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION
    Publication number: 20100164547
    Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.
    Type: Application
    Filed: December 28, 2009
    Publication date: July 1, 2010
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS PVT. LTD.
    Inventors: Luca Ciccarelli, Lorenzo Cali, Massimiliano Innocenti, Claudio Mucci, Valentina Nardone, Matteo Pizzotti, Pankaj Rohilla