Abstract: Aspects of the disclosure relate to high-security digital payment systems with instant activation. The systems may include multiple stages of authorization. The multiple stages of authorization may include increasing thresholds of criteria. The system may also include multiple payment instruments with seamless digital wallet integration.

Abstract: Aspects of the disclosure relate to high-security digital payment systems with instant activation. The systems may include multiple stages of authorization. The multiple stages of authorization may include increasing thresholds of criteria. The system may also include multiple payment instruments with seamless digital wallet integration.

Abstract: Aspects of the disclosure relate to high-security digital payment systems with instant activation. The systems may include multiple stages of authorization. The multiple stages of authorization may include increasing thresholds of criteria. The system may also include multiple payment instruments with seamless digital wallet integration.

Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.

Abstract: A system for managing risk associated with a full-service agreement (FSA) for at least one wind turbine is provided. The system includes a memory device configured to store data including at least a plurality of service reports regarding the at least one wind turbine and a processor unit coupled to the memory device. The processor unit includes a programmable hardware component that is programmed. The processor unit is configured to analyze, by a text-mining system, text in the plurality of service reports to output failure information regarding the at least one wind turbine, receive, by a top-down simulator, the failure information from the text-mining system to perform a simulation that generates a distribution model, and receive, by a bottom-up simulator, the failure information from the text-mining system to perform a simulation that generates an extrapolation model.

Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.

Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.

Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.

Abstract: An interlock assembly comprising: an interlock plate comprising at least one slot disposed about a central portion thereof, a first locking tab disposed perpendicular to a first side of the interlock plate, and a second locking tab disposed perpendicular to a second side of the interlock plate; and a base disposed adjacent to a bottom surface of the interlock plate, the base comprising at least one perturbation disposed on a surface of the base opposite to the bottom surface of the interlock plate, such that the perturbation is disposed within the slot of the interlock plate, thereby providing the interlock plate with reciprocating movement in relation to the base.

Abstract: Switch apparatus is disclosed. The switch apparatus has an enclosure, having a openable cover, a switch disposed within the enclosure, a handle in operative communication with the switch, a spring in biasing communication with the handle, and interlocking members. The interlocking members, the handle, the biasing spring and the switch having positions relative to each other such that the interlocking members lock the cover in a closed position in response to the handle being biased toward an OFF position, and the switch contacts being closed. Further disclosed is a method for unlocking a closed cover of a switch apparatus. A spring biased handle is changed to an OFF biased position from an ON biased position passing through a non-biased position. Subsequent thereto, a switch being changed from a closed circuit to an open circuit position. Subsequent thereto, interlocking members are changed from an interlocked to a non-interlocked position.

Abstract: An interlock assembly comprising: an interlock plate comprising at least one slot disposed about a central portion thereof, a first locking tab disposed perpendicular to a first side of the interlock plate, and a second locking tab disposed perpendicular to a second side of the interlock plate; and a base disposed adjacent to a bottom surface of the interlock plate, the base comprising at least one perturbation disposed on a surface of the base opposite to the bottom surface of the interlock plate, such that the perturbation is disposed within the slot of the interlock plate, thereby providing the interlock plate with reciprocating movement in relation to the base

Abstract: Switch apparatus is disclosed. The switch apparatus has an enclosure, having a openable cover, a switch disposed within the enclosure, a handle in operative communication with the switch, a spring in biasing communication with the handle, and interlocking members. The interlocking members, the handle, the biasing spring and the switch having positions relative to each other such that the interlocking members lock the cover in a closed position in response to the handle being biased toward an OFF position, and the switch contacts being closed. Further disclosed is a method for unlocking a closed cover of a switch apparatus. A spring biased handle is changed to an OFF biased position from an ON biased position passing through a non-biased position. Subsequent thereto, a switch being changed from a closed circuit to an open circuit position. Subsequent thereto, interlocking members are changed from an interlocked to a non-interlocked position.

Abstract: Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.

Abstract: A housing for a circuit breaker motor operating mechanism is disclosed. The housing comprises a base having a plurality of walls connected to a floor thereby defining an interior volume; a cover hingedly attached to one wall of the plurality of walls; and a locking device including a first member connected to the base and a second member connected to the cover and engaged to the first member, the locking device positively securing the cover to the base thereby enclosing the interior volume.