Abstract: In a pulse width modulated read signal channel for an optical disk drive, a data-transition threshold is maintained for data detection by a threshold tracking circuit that estimates the amplitude centerline data-transition threshold from the most recent maximum and minimum values of the read signal waveform. To improve the accuracy of the response of the centerline estimator, the threshold is increased or decreased based on the phase error at each read signal transition through the data-transition threshold. In addition, defects in the optical recording media are detected, and a defect present signal is used to inhibit the transition phase error input to the centerline estimator. This prevents the estimator from moving the threshold to an incorrect stable level. In addition, the defect present signal boosts the error feedback in the centerline estimator. The estimator then more quickly follows the read signal waveform.

Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.

Abstract: A system for encoding and decoding binary data in a data transmission system, such as a magnetic or optical data storage channel. The encoding process is implemented as a two-step RLL coding procedure wherein the original user bit data are first encoded as an asymmetric RLL code signal at a reduced clock rate and then translated to a second even-spaced RLL code signal suitable for recording to a data storage medium at a full-speed clock rate. The system also provides for recovering suitable even-spaced RLL codes recorded at a full-speed clock rate, translating the recovered even-spaced RLL code signal to an asymmetric RLL code signal at a reduced clock rate, and then decoding the asymmetric RLL code signal to recover the original user bit data. A preferred embodiment uses a rate 2/5 (2, 16, 2) even-spaced RLL code at a full-speed clock rate and a rate 4/5 (0,7; 1,8) asymmetric RLL code at a half-speed clock rate.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A variable sampling-rate digital channel phase detector for reading synchronous data recordings from magnetic or optical media. All-digital implementation allows multiplexing of several parallel channels on a single monolithic chip for tape storage systems or other magnetic or optical data storage systems. The ASDD channel signal processing is entirely digital and includes A/D converter, digital filter and equalizer, digital differentiator and zero-crossing detector, peak amplitude estimator, zero-crossing qualifier and zero-crossing position (phase) estimator. The ASDD input is an analog waveform and the output includes two flags for qualified negative and positive waveform threshold-crossings and a digital signal encoding a waveform threshold-crossing position within the current sampling clock interval. The ASDD operates over a wide continuous range of channel data rates and provides accurate phase detection at relatively low sampling rates.