Patents by Inventor Panupong Jaipan

Panupong Jaipan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079166
    Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first device structure on a first substrate, a first laser liftoff layer on the first device structure, a protective layer on the first laser liftoff layer, and a second substrate on the protective layer. The method includes de-attaching, through applying radiation on the first laser liftoff layer, the protective layer from the first laser liftoff layer, with a first surface of the second substrate remaining in contact with a second surface of the protective layer. The protective layer is transparent to the radiation.
    Type: Application
    Filed: July 26, 2024
    Publication date: March 6, 2025
    Inventors: Panupong JAIPAN, Matthew BARON, Kandabara TAPILY, Ilseok SON, Arkalgud SITARAM, Yohei YAMASHITA, Yasutaka MIZOMOTO, Yoshihiro TSUTSUMI, Yoshihiro KONDO
  • Publication number: 20250054904
    Abstract: A method of processing a substrate that includes: forming an infrared (IR) absorbing separation layer over a first substrate; forming one or more layers over the IR absorbing separation layer; bonding the first substrate and a second substrate at a bonding interface between the one or more layers and the second substrate using a direct bonding technique to form a wafer stack; exposing the wafer stack to an infrared (IR) light irradiation to separate the first substrate from the one or more layers.
    Type: Application
    Filed: August 8, 2024
    Publication date: February 13, 2025
    Inventors: Panupong JAIPAN, Kevin RYAN, Ilseok SON, Arkalgud SITARAM, Yohei YAMASHITA, Yasutaka MIZOMOTO, Yoshihiro TSUTSUMI, Yoshihiro KONDO
  • Publication number: 20240243006
    Abstract: In some implementations, a method may include providing a silicon on insulator (SOI) substrate having a first semiconductor layer, a buried oxide layer over the first semiconductor region, and a second semiconductor region over the buried oxide, the second semiconductor region having a plurality of recesses exposing the underlying buried oxide, each recess having a shape and size configured to accommodate a die. In addition, the device may include bonding a plurality of semiconductor dies to the buried oxide through the plurality of recesses.
    Type: Application
    Filed: November 10, 2023
    Publication date: July 18, 2024
    Inventors: Scott Lefevre, Arkalgud Sitaram, Kevin Ryan, Ilseok Son, Panupong Jaipan