Patents by Inventor Pao-Cheng Chiu
Pao-Cheng Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985645Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.Type: GrantFiled: July 18, 2017Date of Patent: May 29, 2018Assignee: MEDIATEK INC.Inventors: Pao-Cheng Chiu, Hung-Yi Hsieh
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Publication number: 20180048326Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.Type: ApplicationFiled: July 18, 2017Publication date: February 15, 2018Inventors: Pao-Cheng Chiu, Hung-Yi Hsieh
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Patent number: 9154152Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k?1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k?1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.Type: GrantFiled: December 19, 2014Date of Patent: October 6, 2015Assignee: MEDIATEK INC.Inventors: Pao-Cheng Chiu, Wei-Hsin Tseng
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Publication number: 20150263756Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k?1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k?1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.Type: ApplicationFiled: December 19, 2014Publication date: September 17, 2015Inventors: Pao-Cheng CHIU, Wei-Hsin TSENG
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Publication number: 20150131811Abstract: A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal has a first signal segment followed by a second signal segment, and a voltage level of the first signal segment is unknown; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit; wherein a voltage of the supply power is settle before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.Type: ApplicationFiled: January 21, 2015Publication date: May 14, 2015Inventors: Tsung-Kai Kao, Pao-Cheng Chiu, Chien-Ming Chen
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Patent number: 9008247Abstract: A communication circuit and a communication device are provided. The communication circuit includes first, second, and third RF transceivers, first and second baseband transceivers, and first and second modem circuits. The first and second RF transceivers are configured to down-convert first and second RF signals for MIMO. The third RF transceiver is configured to down-convert a third RF signal for a second telecommunication technology. The first baseband transceiver is configured to digitize the down-converted first RF signal to output a first baseband signal. The second baseband transceiver is configured to digitize one of the down-converted second or third RF signals according to a selection signal to output a second baseband signal. The first modem circuit is configured to digitally process the first and second baseband signals using the MIMO technology. The second modem circuit is configured to digitally process the second baseband signal using the second telecommunication technology.Type: GrantFiled: June 7, 2013Date of Patent: April 14, 2015Assignee: MediaTek Inc.Inventors: Wei-Cheng Tang, Juiyuan Tsai, Pao-Cheng Chiu
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Publication number: 20140362936Abstract: A communication circuit and a communication device are provided. The communication circuit includes first, second, and third RF transceivers, first and second baseband transceivers, and first and second modem circuits. The first and second RF transceivers are configured to down-convert first and second RF signals for MIMO. The third RF transceiver is configured to down-convert a third RF signal for a second telecommunication technology. The first baseband transceiver is configured to digitize the down-converted first RF signal to output a first baseband signal. The second baseband transceiver is configured to digitize one of the down-converted second or third RF signals according to a selection signal to output a second baseband signal. The first modem circuit is configured to digitally process the first and second baseband signals using the MIMO technology. The second modem circuit is configured to digitally process the second baseband signal using the second telecommunication technology.Type: ApplicationFiled: June 7, 2013Publication date: December 11, 2014Applicant: Media Tek Inc.Inventors: Wei-Cheng TANG, Juiyuan TSAI, Pao-Cheng CHIU
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Patent number: 7973576Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.Type: GrantFiled: May 21, 2008Date of Patent: July 5, 2011Assignee: Mediatek Inc.Inventor: Pao-Cheng Chiu
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Patent number: 7948411Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.Type: GrantFiled: May 7, 2010Date of Patent: May 24, 2011Assignee: Mediatek Inc.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Publication number: 20110116652Abstract: A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal comprises a first signal segment followed by a second signal segment; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit and selectively generating an output signal according to the output control signal; wherein the supply power is turned on before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Inventors: Tsung-Kai Kao, Pao-Cheng Chiu, Chien-Ming Chen
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Patent number: 7936180Abstract: The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.Type: GrantFiled: November 6, 2008Date of Patent: May 3, 2011Assignee: Mediatek Inc.Inventors: Kuan-Hua Chao, Chih-Chien Hung, Pao-Cheng Chiu
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Patent number: 7924062Abstract: A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.Type: GrantFiled: July 15, 2009Date of Patent: April 12, 2011Assignee: Mediatek Inc.Inventor: Pao-Cheng Chiu
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Publication number: 20110012644Abstract: A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.Type: ApplicationFiled: July 15, 2009Publication date: January 20, 2011Applicant: MEDIATEK INC.Inventor: Pao-Cheng Chiu
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Publication number: 20100225515Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.Type: ApplicationFiled: May 7, 2010Publication date: September 9, 2010Applicant: MEDIATEK INC.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Patent number: 7768306Abstract: A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled to a second fixed voltage. The low voltage transistor has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage data signal, and a third terminal. The high voltage transistor has a first terminal coupled to the third terminal of the low voltage transistor, a second terminal coupled to a bias source, and a third terminal coupled to the output.Type: GrantFiled: September 20, 2006Date of Patent: August 3, 2010Assignee: Mediatek Inc.Inventor: Pao-Cheng Chiu
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Patent number: 7741984Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.Type: GrantFiled: September 24, 2008Date of Patent: June 22, 2010Assignee: Mediatek Inc.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Patent number: 7738408Abstract: A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.Type: GrantFiled: March 17, 2005Date of Patent: June 15, 2010Assignee: Realtek Semiconductor Corp.Inventors: Pao-Cheng Chiu, Chen-Chih Huang
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Publication number: 20100073209Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Applicant: MEDIATEK INC.Inventors: Zwei-Mei LEE, Kang-Wei HSUEH, Ya-Lun YANG, Hung-Sung LI, Pao-Cheng CHIU
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Publication number: 20090289673Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: MEDIATEK INC.Inventor: Pao-Cheng CHIU
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Publication number: 20090195288Abstract: The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.Type: ApplicationFiled: November 6, 2008Publication date: August 6, 2009Applicant: MEDIATEK INC.Inventors: Kuan-Hua Chao, Chih-Chien Hung, Pao-Cheng Chiu