Abstract: A fabrication method and a structure of a flash memory. Several first shallow trench isolations and second shallow trench isolations are formed in a memory circuit region and a peripheral circuit region of a substrate, respectively. The first shallow trench isolations are shallower than the second shallow trench isolations. Several gates are formed along a direction perpendicular to the substrate in the memory circuit region. A self-aligned source region process is performed to remove the isolation layer within every other first shallow trench isolations between the gates. A common source region and a column of separate drain regions are thus alternatively formed between the gates. The drain regions in the same column are isolated by the first shallow trench isolations.

Abstract: A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the deposition of an isolation layer on the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and an ONO dielectric layer are formed in the trenches, respectively. A doped polysilicon layer is then formed on the silicon substrate to fill the trenches, followed by the removal of a portion of the doped polysilicon layer to form two controlling gates in the active area. Next, a self-alignment common source is formed between the two controlling gates and a plurality of spacers are formed on either side of each controlling gate. Finally, a silicide layer is formed on the surfaces of the controlling gates and the common source.

Abstract: A fabrication method and a structure of a flash memory. Several first shallow trench isolations and second shallow trench isolations are formed in a memory circuit region and a peripheral circuit region of a substrate, respectively. The first shallow trench isolations are shallower than the second shallow trench isolations. Several gates are formed along a direction perpendicular to the substrate in the memory circuit region. A self-aligned source region process is performed to remove the isolation layer within every other first shallow trench isolations between the gates. A common source region and a column of separate drain regions are thus alternatively formed between the gates. The drain regions in the same column are isolated by the first shallow trench isolations.

Abstract: A cell voltage balancer for balancing the voltage of the first cell and the voltage of the second cell. The cell voltage balancer includes the first input terminal, the second input terminal and the third input terminal. The cell voltage balancer includes a transformer, the first switch and the second switch. The transformer includes a primary winding and a secondary winding. The first switch and the primary winding are serially connected between the first input terminal and the second input terminal. The second switch and the secondary winding are serially connected between the second input terminal and the third input terminal. The first switch and the second switch are switched on and off alternatively. While the first switch is on and the second switch is off, the primary winding stores energy of the first cell in the transformer. On the contrary, the secondary winding recovers energy stored in the transformer into the second cell.