Patents by Inventor Pao-Hei Chang Chin

Pao-Hei Chang Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating a stacked chip package
    Patent number: 6541871
    Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: April 1, 2003
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang
  • Method for fabricating a stacked chip package
    Publication number: 20020094605
    Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.
    Type: Application
    Filed: March 18, 2002
    Publication date: July 18, 2002
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang
  • Method for fabricating a stacked chip package
    Patent number: 6387728
    Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface, of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step the cycle time may be reduced thereby cutting down the production cost.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: May 14, 2002
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Ming Pai, Chung-Hao Lee, Pao-Hei Chang Chin, Meng-Hui Lin, Song-Fei Wang