Patents by Inventor Pao-Hwa Chou

Pao-Hwa Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8216648
    Abstract: A film formation method includes setting a target object at a temperature of 150 to 550° C., the target object being placed inside the process container configured to hold a vacuum state therein, and then, repeating a cycle alternately including a first supply step and a second supply step a plurality of times to form a silicon nitride film on the target object. The first supply step is a step of supplying monochlorosilane gas as an Si source into the process container while setting the process container at a pressure of 66.65 to 666.5 Pa therein. The second supply step is a step of supplying a nitrogen-containing gas as a nitriding gas into the process container.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Matsunaga, Keisuke Suzuki, Jaehyuk Jang, Pao-Hwa Chou, Masato Yonezawa, Masayuki Hasegawa, Kazuhide Hasebe
  • Publication number: 20120164327
    Abstract: A film-forming method includes forming a tungsten film or a tungsten oxide film on an object to be processed, forming a seed layer on the tungsten film or the tungsten oxide film, and forming a silicon oxide film on the seed layer, wherein the seed layer formed on the tungsten film or the tungsten oxide film is formed by heating the object to be processed and supplying an aminosilane-based gas to a surface of the tungsten film or the tungsten oxide film.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 28, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jun SATO, Pao-Hwa Chou
  • Publication number: 20120164847
    Abstract: A control unit heats a reaction pipe to a load temperature by controlling a temperature-raising heater 16, and then makes semiconductor wafers received in the reaction pipe. Next, the control unit heats the reaction pipe in which the semiconductor wafers are received to a film formation temperature by controlling the temperature-raising heater, and then forms thin films on the semiconductor wafers by supplying a film forming gas into the reaction pipe from a process gas introducing pipe. Also, the control unit sets the load temperature to a temperature higher than the film formation temperature.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 28, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshiyuki IKEUCHI, Pao-Hwa CHOU, Kazuya YAMAMOTO, Kentarou SERA
  • Patent number: 8178448
    Abstract: Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Nobutake Nodera, Masanobu Matsunaga, Kazuhide Hasebe, Koto Umezawa, Pao-Hwa Chou
  • Patent number: 8168375
    Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a multi-layered film including a resist film on the first film; forming a patterned resist film having a preset pattern by patterning the resist film by photolithography; forming a silicon oxide film different from the first film on the patterned resist film and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; etching the silicon oxide film to thereby form a sidewall spacer on a sidewall of the patterned resist film; removing the patterned resist film; and processing the first film by using the sidewall spacer as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 1, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 8080290
    Abstract: A film formation method is used for forming a silicon nitride film on a target substrate by repeating a plasma cycle and a non-plasma cycle a plurality of times, in a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas and communicating with an exciting mechanism for exciting the second process gas to be supplied. The method includes obtaining a relation formula or relation table that represents relationship of a cycle mixture manner of the plasma cycle and the non-plasma cycle relative to a film quality factor of the silicon nitride film; determining a specific manner of the cycle mixture manner based on a target value of the film quality factor with reference to the relation formula or relation table; and arranging the film formation process in accordance with the specific manner.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: December 20, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Nobutake Nodera, Masanobu Matsunaga, Jun Satoh, Pao-Hwa Chou
  • Publication number: 20110281443
    Abstract: The film formation method includes transferring an object to be processed into a process chamber; controlling a temperature of the object to be processed to be equal to or lower than 350° C.; and supplying an aminosilane gas as a Si source gas and an oxidizing gas into the process chamber, wherein the oxidizing gas consists of a first oxidizing gas comprising at least one selected from the group consisting of an O2 gas and an O3 gas, and a second oxidizing gas comprising at least one selected from the group consisting of a H2O gas and a H2O2 gas, thereby forming a silicon oxide film on a surface of the object to be processed.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 17, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Pao-Hwa CHOU, Kota UMEZAWA, Yosuke WATANABE, Masayuki HASEGAWA
  • Patent number: 8034673
    Abstract: A film formation method for a semiconductor process performs a film formation process to form a silicon-containing insulating film doped with a metal on a target substrate, in a process field inside a process container configured to be selectively supplied with a silicon source gas and a metal source gas. The method includes forming a first insulating thin layer by use of a chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas; then, forming a first metal thin layer by use of a chemical reaction of the metal source gas, while maintaining a shut-off state of supply of the silicon source gas; and then, forming a second insulating thin layer by use of the chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kentaro Kadonaga, Yamato Tonegawa, Pao-Hwa Chou, Kazuhide Hasebe, Tetsuya Shibata
  • Publication number: 20110241128
    Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A. Conti
  • Publication number: 20110241085
    Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A. Conti
  • Publication number: 20110237082
    Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 8025931
    Abstract: A method for using a film formation apparatus performs a first film formation process, while supplying a first film formation gas into a process field inside a process container, thereby forming a first thin film on a first target substrate inside the process field. After unloading the first target substrate from the process container, the method performs a cleaning process of an interior of the process container, while supplying a cleaning gas into the process field, and generating plasma of the cleaning gas by an exciting mechanism. Then, the method performs a second film formation process, while supplying a second film formation gas into the process field, thereby forming a second thin film on a target substrate inside the process field. The second film formation process is a plasma film formation process that generates plasma of the second film formation gas by the exciting mechanism.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: September 27, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe
  • Patent number: 7989354
    Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 2, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 7964241
    Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas or oxynitriding gas, a third process gas containing a boron-containing gas, and a fourth process gas containing a carbon hydride gas. A first step performs supply of the first process gas and a preceding gas, which is one of the third and fourth process gases, while stopping supply of the second process gas and a succeeding gas, which is the other of the third and fourth process gases. A second step performs supply of the succeeding gas, while stopping supply of the second process gas and the preceding gas. A third step performs supply of the second process gas while stopping supply of the first process gas.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: June 21, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Pao-Hwa Chou, Kota Umezawa, Kentaro Kadonaga, Hao-Hsiang Chang
  • Patent number: 7959733
    Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 14, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Pao-Hwa Chou, Chaeho Kim
  • Publication number: 20110129618
    Abstract: A method for using a vertical film formation apparatus includes performing a coating process inside the process container without product target objects present therein to cover an inner surface of the process container with a coating film, and then performing a film formation process inside the process container accommodating the holder with the product target objects placed thereon to form a predetermined film on the product target objects. The coating process alternately supplies the first and second process gases into the process container without turning either of the first and second process gases into plasma. The film formation process alternately supplies the first and second process gases into the process container while turning at least one of the first and second process gases into plasma.
    Type: Application
    Filed: November 26, 2010
    Publication date: June 2, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masanobu MATSUNAGA, Pao-Hwa Chou, Masato Yonezawa, Masayuki Hasegawa, Kazuhide Hasebe
  • Publication number: 20110129619
    Abstract: A film formation method includes setting a target object at a temperature of 150 to 550° C., the target object being placed inside the process container configured to hold a vacuum state therein, and then, repeating a cycle alternately including a first supply step and a second supply step a plurality of times to form a silicon nitride film on the target object. The first supply step is a step of supplying monochlorosilane gas as an Si source into the process container while setting the process container at a pressure of 66.65 to 666.5 Pa therein. The second supply step is a step of supplying a nitrogen-containing gas as a nitriding gas into the process container.
    Type: Application
    Filed: November 26, 2010
    Publication date: June 2, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masanobu Matsunaga, Keisuke Suzuki, Jaehyuk Jang, Pao-Hwa Chou, Masato Yonezawa, Masayuki Hasegawa, Kazuhide Hasebe
  • Publication number: 20100304574
    Abstract: Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 2, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Nobutake NODERA, Masanobu Matsunaga, Kazuhide Hasebe, Koto Umezawa, Pao-Hwa Chou
  • Patent number: 7758920
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a purge gas, a first process gas containing a silane family gas, and a second process gas containing a gas selected from the group consisting of nitriding, oxynitriding, and oxidizing gases. This method alternately includes first to fourth steps. The first, second, third, and fourth steps perform supply of the first process gas, purge gas, second process gas, and purge gas, respectively, while stopping supply of the other two gases. The process field is continuously vacuum-exhausted over the first to fourth steps through an exhaust passage provided with an opening degree adjustment valve. An opening degree of the valve in the first step is set to be 5 to 95% of that used in the second and fourth steps.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: July 20, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Mitsuhiro Okada, Pao-Hwa Chou, Jun Ogawa, Chaeho Kim, Kohei Fukushima, Toshiki Takahashi, Jun Sato
  • Patent number: 7754622
    Abstract: Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: July 13, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe, Shigeru Nakajima, Yasushi Akasaka, Mitsuaki Iwashita, Reiji Niino