Patents by Inventor Pao-Kang Niu
Pao-Kang Niu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8217520Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.Type: GrantFiled: March 12, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Bill Kiang, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu
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Patent number: 7843058Abstract: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.Type: GrantFiled: October 30, 2007Date of Patent: November 30, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Haw Tsao, Liang-Chen Lin, Pao-Kang Niu
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Publication number: 20100164091Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Inventors: Pei-Haw Tsao, Bill Kiang, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu
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Patent number: 7719122Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.Type: GrantFiled: January 11, 2007Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Bill Kiang, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu
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Patent number: 7679180Abstract: An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.Type: GrantFiled: November 7, 2006Date of Patent: March 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu, Bill Kiang
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Patent number: 7659632Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.Type: GrantFiled: November 3, 2006Date of Patent: February 9, 2010Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.Inventors: Pei-Haw Tsao, Bill Kiang, Pao-Kang Niu, Liang-Chen Lin, I-Tai Liu
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Patent number: 7602065Abstract: A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.Type: GrantFiled: March 5, 2008Date of Patent: October 13, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Chun-Hung Chen, Chia-Lun Tsai, Pao-Kang Niu, Shin-Puu Jeng
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Publication number: 20090140391Abstract: A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening.Type: ApplicationFiled: March 5, 2008Publication date: June 4, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Yun Hou, Chun-Hung Chen, Chia-Lun Tsai, Pao-Kang Niu, Shin-Puu Jeng
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Publication number: 20090108429Abstract: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Pei-Haw Tsao, Liang-Chen Lin, Pao-Kang Niu
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Publication number: 20080274569Abstract: A method for forming a semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights and coplanar apices.Type: ApplicationFiled: July 10, 2008Publication date: November 6, 2008Inventors: Pei-Haw Tsao, Pao-Kang Niu, Liang-Chen Lin, I. T. Liu
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Patent number: 7446398Abstract: A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.Type: GrantFiled: August 1, 2006Date of Patent: November 4, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pao-Kang Niu, Pei-Haw Tsao, Hao-Yi Tsai, Yung-Kuan Hsiao, Chung Yu Wang, Shang-Yun Hou, Lin Yu-Ting
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Publication number: 20080169557Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Inventors: Pei-Haw Tsao, Bill Kiang, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu
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Publication number: 20080122086Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.Type: ApplicationFiled: November 3, 2006Publication date: May 29, 2008Inventors: Pei-Haw Tsao, Bill Kiang, Pao-Kang Niu, Liang-Chen Lin, I-Tai Liu
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Publication number: 20080122100Abstract: An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.Type: ApplicationFiled: November 7, 2006Publication date: May 29, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Haw Tsao, Liang-Chen Lin, Pao-Kang Niu, I-Tai Liu, Bill Kiang
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Publication number: 20080054455Abstract: A semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights.Type: ApplicationFiled: August 29, 2006Publication date: March 6, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Haw Tsao, Pao-Kang Niu, Liang-Chen Lin, I. T. Liu
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Publication number: 20080042269Abstract: A bump structure for bonding two substrates together includes a composite structure. The composite structure is formed over a first substrate. The composite structure includes at least one first polymer layer and at least one first metal-containing layer. The bump structure also includes a second metal-containing layer at least partially covering a top surface of the composite structure and extending from the top surface of the composite structure to a surface of the first substrate, wherein the second metal-containing layer is thinner than the first metal-containing layer.Type: ApplicationFiled: August 16, 2006Publication date: February 21, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pao-Kang Niu, Chien-Jung Wang, Chang-Chun Lee
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Publication number: 20080029876Abstract: A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.Type: ApplicationFiled: August 1, 2006Publication date: February 7, 2008Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pao-Kang Niu, Pei-Haw Tsao, Hao-Yi Tsai, Yung-Kuan Hsiao, Chung Yu Wang, Shang-Yun Hou, Lin Yu-Ting
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Publication number: 20080003803Abstract: A method for forming a semiconductor package is provided. In one embodiment, the method comprises providing a semiconductor substrate having at least one bump pad formed thereon. A solder mask layer is provided above the bump pad, the solder mask layer having at least one opening formed therein exposing a portion of the bump pad. A layer of solder wettable material is formed on the exposed surface of the bump pad and the sidewalls and substantially on the comers of the solder mask layer. A solder material is deposited above the layer of solder wettable material and portions of the solder mask layer and the solder material is reflown to create a solder bump.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Pei-Haw Tsao, Pao-Kang Niu, D. J. Perng
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Publication number: 20070042593Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.Type: ApplicationFiled: October 27, 2006Publication date: February 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD,Inventors: Jian-Hsing Lee, Pao-Kang Niu, Ko-Yi Lee
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Patent number: 7148574Abstract: A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edge portion, a second conductive layer having a wire bonding portion and a second edge portion and a plurality of plugs electrically connecting the wiring layer and the wire bonding portion. A conductive structure of an array of metal plugs or a metal damascene structure is formed to connect the first edge portion and the second edge portion, thereby preventing burn out of the first edge portion during an ESD event.Type: GrantFiled: April 14, 2004Date of Patent: December 12, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hsing Lee, Pao-Kang Niu, Ko-Yi Lee