Patents by Inventor Pao-Ling Kuo

Pao-Ling Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6531326
    Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 11, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Ming Chen, Yuh-Da Fan, Pao-Ling Kuo
  • Publication number: 20020013056
    Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.
    Type: Application
    Filed: September 20, 2001
    Publication date: January 31, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Ching-Ming Chen, Yuh-Da Fan, Pao-Ling Kuo
  • Patent number: 6303509
    Abstract: A method for calibrating the wafer transfer system by using an inspection control wafer after plasma etching is described. An inspection control wafer is provided comprising a polysilicon layer overlying an oxide layer on the surface of a semiconductor substrate wherein the polysilicon layer does not cover the oxide layer for a first distance from the edge of the wafer. The inspection control wafer is entered into the wafer transfer system wherein the wafer is transferred to a spin-on-glass etchback chamber wherein the wafer is held by clamps which extend a second distance from the edge of the wafer and wherein there is designed an overlap difference between the first and second distances. The wafer is subjected to a spin-on-glass etchback step and then inspected for damage to the oxide layer. Oxide layer damage occurs if the second distance is less than the first distance by more than the overlap difference. Oxide layer damage indicates the need to recalibrate the wafer transfer system.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: October 16, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Ming Chen, Yuh-Da Fan, Pao-Ling Kuo
  • Patent number: 5454871
    Abstract: An apparatus for applying spin-on-glass material to a wafer under controlled humidity conditions is described, The apparatus comprises a treatment chamber. Within the treatment chamber are a spin-on-glass coater spin table, a plurality of hotplates connected to one another and from the coater spin table by a moving belt, and wafer handlers to transfer wafers onto the coater spin table and onto the moving belt. A dehumidifier is disposed on top of the treatment chamber and a humidity control unit is disposed on top of the dehumidifier through which air is drawn and whereby relative humidity within the treatment chamber can be controlled.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: October 3, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Haw Liaw, Hsin-Chieh Huang, Pao-Ling Kuo
  • Patent number: 5371046
    Abstract: A new method of planarizing an integrated circuit is described. A first coating of a silicate spin-on-glass material is applied to the surface of a patterned conductor layer to be planarized. The spin-on-glass material is applied under low relative humidity, filling the valleys of the irregular structure of the conductor layer. The first spin-on-glass layer is covered with a second coating of the spin-on-glass material also applied under low relative humidity. Then, both first and second spin-on-glass layers are cured. This method provides a uniform spin-on-glass dielectric layer upon which a second conductor layer may now be successfully applied.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: December 6, 1994
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yung-Haw Liaw, Hsin-Chieh Huang, Pao-Ling Kuo