Patents by Inventor Pao-Ming Hsieh
Pao-Ming Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9196597Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.Type: GrantFiled: August 6, 2014Date of Patent: November 24, 2015Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Patent number: 9165900Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: GrantFiled: February 6, 2014Date of Patent: October 20, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
-
Publication number: 20140346670Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.Type: ApplicationFiled: August 6, 2014Publication date: November 27, 2014Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Patent number: 8884424Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.Type: GrantFiled: September 23, 2013Date of Patent: November 11, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Patent number: 8786062Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: GrantFiled: October 14, 2010Date of Patent: July 22, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
-
Publication number: 20140151876Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
-
Publication number: 20140021636Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Patent number: 8569894Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.Type: GrantFiled: January 13, 2011Date of Patent: October 29, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Patent number: 8330267Abstract: A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.Type: GrantFiled: October 28, 2009Date of Patent: December 11, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuang-Hsiung Chen, Pao-Ming Hsieh, Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt
-
Publication number: 20110169150Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.Type: ApplicationFiled: January 13, 2011Publication date: July 14, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
-
Publication number: 20110084370Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: ApplicationFiled: October 14, 2010Publication date: April 14, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: YUAN-CHANG SU, SHIH-FU HUANG, CHIA-CHENG CHEN, CHIA-HSIUNG HSIEH, TZU-HUI CHEN, KUANG-HSIUNG CHEN, PAO-MING HSIEH
-
Publication number: 20110057301Abstract: A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.Type: ApplicationFiled: October 28, 2009Publication date: March 10, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuang-Hsiung Chen, Pao-Ming Hsieh, Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt