Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

Abstract: Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.