Patents by Inventor Pao-Tung Chen

Pao-Tung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11646247
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
  • Publication number: 20230106039
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 11600653
    Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 11552027
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Patent number: 11545443
    Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 11532661
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20210296258
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Patent number: 11037885
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Publication number: 20210159264
    Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
    Type: Application
    Filed: February 3, 2021
    Publication date: May 27, 2021
    Inventors: Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20210082787
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
  • Patent number: 10930699
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Publication number: 20210050303
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Publication number: 20210005558
    Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming WU, Kuan-Liang LIU, Pao-Tung CHEN
  • Patent number: 10867891
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
  • Patent number: 10790240
    Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 10777539
    Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang
  • Publication number: 20200135617
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.
    Type: Application
    Filed: April 23, 2019
    Publication date: April 30, 2020
    Inventors: Yu-Yang Shen, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen
  • Publication number: 20200119074
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20200035743
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Publication number: 20200027860
    Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang