Patents by Inventor Paola Maria Ponzio

Paola Maria Ponzio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210273045
    Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Antonino SCHILLACI, Paola Maria PONZIO, Roberto CAMMARATA
  • Patent number: 11024707
    Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 1, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Schillaci, Paola Maria Ponzio, Roberto Cammarata
  • Publication number: 20190386097
    Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 19, 2019
    Inventors: Antonino SCHILLACI, Paola Maria PONZIO, Roberto CAMMARATA
  • Patent number: 9899508
    Abstract: Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: February 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Schillaci, Paola Maria Ponzio, Alessandro Angelo Alfio Palazzo
  • Patent number: 9508846
    Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: November 29, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Schillaci, Alfonso Patti, Paola Maria Ponzio
  • Publication number: 20150303300
    Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.
    Type: Application
    Filed: March 19, 2015
    Publication date: October 22, 2015
    Inventors: Antonino Schillaci, Alfonso Patti, Paola Maria Ponzio
  • Patent number: 6919252
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 19, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Schillaci, Paola Maria Ponzio
  • Publication number: 20040211984
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Application
    Filed: May 21, 2004
    Publication date: October 28, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino Schillaci, Paola Maria Ponzio
  • Patent number: 6750512
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: June 15, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Schillaci, Paola Maria Ponzio
  • Publication number: 20030075739
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Application
    Filed: September 20, 2002
    Publication date: April 24, 2003
    Applicant: STMICROELECTRONICS S.r.I.
    Inventors: Antonino Schillaci, Paola Maria Ponzio