Patents by Inventor Paolo Amato

Paolo Amato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250239301
    Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
    Type: Application
    Filed: April 10, 2025
    Publication date: July 24, 2025
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
  • Publication number: 20250208950
    Abstract: The present disclosure includes apparatuses, methods, and systems for memory maintenance operations. An embodiment includes a memory having a plurality of groups of memory cells, wherein one of the plurality of groups of memory cells does not have data stored therein and all other ones of the plurality of groups of memory cells have data stored therein, and a controller coupled to the memory and having circuitry configured to determine one of the plurality of groups of memory cells that has data stored therein is a bad group of memory cells, recover the data stored in the bad group of memory cells, program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, and retire the bad group of memory cells.
    Type: Application
    Filed: July 31, 2024
    Publication date: June 26, 2025
    Inventors: Daniele Balluchi, Marco Sforzin, Paolo Amato
  • Publication number: 20250199908
    Abstract: Provided are methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. There is provided a method for encoding data into a beat that can be executed by a digital system to receive the data and construct the beat. The method includes assembling a plurality of words consecutively. The words include a first set of words in which each word has a length W, where W is the beat width. The words further include a second set of words in which each word has a length that is smaller or equal to W. The method further includes constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the words to form the beat.
    Type: Application
    Filed: July 15, 2024
    Publication date: June 19, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Marc SFORZIN, Paolo AMATO
  • Publication number: 20250156272
    Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Inventors: Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri, Marco Sforzin
  • Publication number: 20250148133
    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Danilo Caraccio, Federica Cresci, Alessandro Orlando, Paolo Amato, Angelo Alberto Rovelli, Craig A. Jones, Niccolò Izzo
  • Patent number: 12277969
    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.
    Type: Grant
    Filed: May 10, 2024
    Date of Patent: April 15, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando, Marco Sforzin
  • Patent number: 12277967
    Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: April 15, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
  • Patent number: 12235722
    Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri, Marco Sforzin
  • Patent number: 12222806
    Abstract: Data protection with error correction/detection capabilities can be provided on a cache line basis. When provided on a cache line basis to collectively protect the cache line data, the error correction/detection capabilities can be provided with fewer number of bits (e.g., error correction code (ECC) and/or cyclic redundancy check (CRC) bits) as compared to providing the same error correction/detection capabilities individually on a subset of the cache line data.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato
  • Publication number: 20250046369
    Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the array of memory cells using a reference voltage and determine an amount by which to adjust the reference voltage used to sense the codeword based on an estimated weight of the original codeword, a mean of threshold voltage values of each memory cell of the sensed codeword, and a total quantity of memory cells of the sensed codeword. The circuitry can further be configured to adjust the reference voltage used to sense the codeword by the determined amount.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Marco Sforzin, Paolo Amato, Luca Barletta, Marco Pietro Ferrari, Antonino Favano
  • Patent number: 12210413
    Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: January 28, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. McCrate, Marco Sforzin, Paolo Amato, Lingming Yang, Nevil N. Gajera
  • Publication number: 20250028486
    Abstract: Methods, systems, and devices for log management maintenance operation and command are described. A method may include receiving, at a memory system, a command associated with maintenance for the memory system and indicating to initiate collecting values of a parameter, storing a value of the parameter, and transmitting, to a host system, a message indicating an availability of the value of the parameter based at least in part on storing the value of the parameter. An additional method may include transmitting, to a host system, a message indicating that a quantity of errors for an address of an address space associated with the memory system satisfies a threshold, receiving a command associated with maintenance for the memory system and indicating a retirement of the address, and retiring the address for the address space associated with the memory system based at least in part on receiving the command.
    Type: Application
    Filed: August 13, 2024
    Publication date: January 23, 2025
    Inventors: Danilo Caraccio, Paolo Amato, Daniele Balluchi
  • Patent number: 12197631
    Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Federica Cresci, Alessandro Orlando, Paolo Amato, Angelo Alberto Rovelli, Craig A. Jones, Niccolò Izzo
  • Patent number: 12189478
    Abstract: A system and method for memory error recovery in compute express link (CXL) components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 7, 2025
    Inventors: Marco Sforzin, Paolo Amato, Daniele Balluchi
  • Publication number: 20240429944
    Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.
    Type: Application
    Filed: August 23, 2024
    Publication date: December 26, 2024
    Inventors: Marco Sforzin, Paolo Amato, Yang Lu
  • Publication number: 20240428833
    Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. The circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. The circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a Pearson detector, and determine the originally programmed data of the codeword using the Pearson detector.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Inventors: Marco Sforzin, Paolo Amato, Luca Barletta, Marco Pietro Ferrari, Antonino Favano
  • Publication number: 20240427526
    Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Inventors: Nicola Del Gatto, Emanuele Confalonieri, Paolo Amato, Patrick Estep, Stephen S. Pawlowski
  • Publication number: 20240411644
    Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
    Type: Application
    Filed: August 23, 2024
    Publication date: December 12, 2024
    Inventors: Marco Sforzin, Paolo Amato, Joseph M. McCrate
  • Publication number: 20240411451
    Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Inventors: Marco Sforzin, Paolo Amato, Daniele Balluchi
  • Publication number: 20240386956
    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.
    Type: Application
    Filed: May 10, 2024
    Publication date: November 21, 2024
    Inventors: Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando, Marco Sforzin