Patents by Inventor Paolo Amato

Paolo Amato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transaction metadata
    Patent number: 10733046
    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Marco Sforzin, Paolo Amato, Danilo Caraccio
  • DATA RELOCATION IN HYBRID MEMORY
    Publication number: 20200233585
    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Inventors: Emanuele Confalonieri, Marco Dallabora, Paolo Amato, Danilo Caraccio, Daniele Balluchi
  • SUB-THRESHOLD VOLTAGE LEAKAGE CURRENT TRACKING
    Publication number: 20200227094
    Abstract: An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Paolo Fantini, Paolo Amato, Marco Sforzin
  • ERROR CORRECTION USING HIERARCHICAL DECODERS
    Publication number: 20200226020
    Abstract: Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Paolo Amato, Marco Sforzin
  • Latency-based storage in a hybrid memory system
    Patent number: 10705963
    Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • Latency-based storage in a hybrid memory system
    Patent number: 10705747
    Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • MEMORY MANAGEMENT UTILZING BUFFER RESET COMMANDS
    Publication number: 20200210103
    Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Marco Sforzin, Paolo Amato
  • DATA RELOCATION IN MEMORY HAVING TWO PORTIONS OF DATA
    Publication number: 20200183828
    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. Circuitry is configured to relocate the data of the first portion that is associated with one of the first number of logical block addresses to one of the two physical blocks of cells that don't have data stored therein, and relocate the data of the second portion that is associated with one of the second number of logical block addresses to the other one of the two physical blocks of cells that don't have data stored therein.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Paolo Amato, Daniele Balluchi
  • Dedicated read voltages for data structures
    Patent number: 10658034
    Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra, Paolo Amato
  • DATA STATE SYNCHRONIZATION
    Publication number: 20200152267
    Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Marco Dallabora, Paolo Amato, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri
  • Data relocation in hybrid memory
    Patent number: 10649665
    Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Emanuele Confalonieri, Marco Dallabora, Paolo Amato, Danilo Caraccio, Daniele Balluchi
  • DEDICATED READ VOLTAGES FOR DATA STRUCTURES
    Publication number: 20200143880
    Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Marco Sforzin, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra, Paolo Amato
  • Dedicated commands for memory operations
    Patent number: 10622065
    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Paolo Amato, Graziano Mirichigni, Danilo Caraccio, Marco Sforzin, Marco Dallabora
  • Sub-threshold voltage leakage current tracking
    Patent number: 10607664
    Abstract: An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Paolo Amato, Marco Sforzin
  • Error correction using hierarchical decoders
    Patent number: 10606694
    Abstract: Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Program operations in memory
    Patent number: 10600456
    Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli, Marco Dallabora
  • Auto-referenced memory cell read techniques
    Patent number: 10600480
    Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Graziano Mirichigni, Paolo Amato, Federico Pio, Alessandro Orlando, Marco Sforzin
  • DATA STATE SYNCHRONIZATION
    Publication number: 20200082900
    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Paolo Amato, Marco Dallabora, Daniele Balluchi, Danilo Caraccio, Emanuele Confalonieri
  • DEDICATED COMMANDS FOR MEMORY OPERATIONS
    Publication number: 20200082883
    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Daniele Balluchi, Paolo Amato, Graziano Mirichigni, Danilo Caraccio, Marco Sforzin, Marco Dallabora
  • HYBRID MEMORY SYSTEM INTERFACE
    Publication number: 20200081853
    Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Danilo Caraccio, Marco Dallabora, Daniele Balluchi, Paolo Amato, Luca Porzio