Abstract: An Automatic Identification System—AIS—receiver comprising at least one processing section (PS1, PS2) for synchronizing, demodulating and detecting AIS messages contained in a received signal, said processing steps being carried out separately for a plurality of frequency sub-bands (SB1, SB2, SB3) spanning an AIS channel (CH1, CH2); the receiver being characterized in that: said sub-bands overlap with each others; and said or each processing section is adapted for synchronizing, demodulating and detecting said AIS messages within each sub-band on the basis of timing error and carrier frequency estimations obtained from filtered replicas of said received signal, propagating along respective auxiliary signal paths.

Abstract: A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.

Abstract: A configurable Turbo-LDPC decoder comprising: A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory.

Abstract: An Automatic Identification System—AIS—receiver comprising at least one processing section (PS1, PS2) for synchronizing, demodulating and detecting AIS messages contained in a received signal, said processing steps being carried out separately for a plurality of frequency sub-bands (SB1, SB2, SB3) spanning an AIS channel (CH1, CH2); the receiver being characterized in that: said sub-bands overlap with each others; and said or each processing section is adapted for synchronizing, demodulating and detecting said AIS messages within each sub-band on the basis of timing error and carrier frequency estimations obtained from filtered replicas of said received signal, propagating along respective auxiliary signal paths.