Abstract: In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.