Abstract: A remote control system is configured to support communication between a first environment having a first neutron radiation level and a second environment having a second neutron radiation level includes a first computing device and a second computing device. The first computing device is configured to control a treatment system in the first environment. The second computing device is configured to issue commands in the second environment for the treatment system. The first computing device is further configured to determine whether to enable or disable a function supported by the treatment system, determine whether there is pending time-sensitive data to transmit, and periodically transmit a first radiation therapy data collected in the first environment and a first interrupt to the second computing device in a servo loop.

Abstract: A remote control system is configured to support communication between a first environment having a first neutron radiation level and a second environment having a second neutron radiation level includes a first computing device and a second computing device. The first computing device is configured to control a treatment system in the first environment. The second computing device is configured to issue commands in the second environment for the treatment system. The first computing device is further configured to determine whether to enable or disable a function supported by the treatment system, determine whether there is pending time-sensitive data to transmit, and periodically transmit a first radiation therapy data collected in the first environment and a first interrupt to the second computing device in a servo loop.

Abstract: A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement capability are provided in a single module. The module comprises an input/output switch matrix selectively coupled to a low frequency filter block and a high frequency filter block. Each filter block may be used for either source or measurement. The filter blocks are selectively coupled to a plurality of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The ADCs and DACs are coupled to a digital interface.

Abstract: A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, synchronously stop adding fill-in clock pulses, and track the request for data acquisition.

Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Abstract: An analog test instrument used in an apparatus for testing electronic devices has multiple analog modules for supplying test signals to analog pins of a device under test and receiving response signals from the analog pins. The analog modules may be of the same type or of different types. The analog test instrument also has programmable devices that control in an independent manner the triggering, clocking, and generation of the test signals supplied by each of the analog modules, so that test signals of various timings, speeds and waveforms may be generated.

Abstract: A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement capability are provided in a single module. The module comprises an input/output switch matrix selectively coupled to a low frequency filter block and a high frequency filter block. Each filter block may be used for either source or measurement. The filter blocks are selectively coupled to a plurality of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The ADCs and DACs are coupled to a digital interface.

Abstract: A module comprising a programmable digital interface coupled to a signal source circuit and to a signal measurement circuit. The digital interface is implemented using one or more field programmable gate arrays (FPGAs) that provides for transmission of test measurement data to control hardware, and the reception of test source data from the control hardware. An FPGA may also be used to control the selection of operational parameters for functional blocks in the source and measurement circuits in the module.

Abstract: A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, synchronously stop adding fill-in clock pulses, and track the request for data acquisition.

Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Abstract: A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values; storing the n pulses addresses prior to the current pulse address; building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m.sup.n+1 pulse shapes. Also, apparatus issuing high speed pulses of programmable length.