Abstract: A method for current measurement in a switching converter is described herein. In accordance with one embodiment, the method includes switching a first transistor on and off in accordance with a logic signal, wherein a load current passes through the first transistor while it is switched on. The method further includes providing—by a second transistor—a sense current that is indicative of the load current, wherein the second transistor is coupled to the first transistor so that the first and the second transistors are switched on and off simultaneously. Further, the method includes determining an end of a switch-on phase of the second transistor, and providing a current sense signal that represents the sense current between a first time instant, which corresponds to the determined end of the switch-on phase, and a second time instant, at which the logic signal signals a switch-off of the first transistor.

Abstract: A circuit which may be uses as an intelligent semiconductor switch is described herein. In accordance with one embodiment, the circuit includes a high—side power transistor having a load current path coupled between a supply node and an output node, which is configured to provide, during operation, a load current to a load. The circuit further includes a gate driver circuit coupled to a control electrode of the power transistor, and a first stage of an overcurrent protection circuit coupled to the control electrode of the power transistor and configured to drive the control electrode such that a voltage drop across the load current path of the power transistor increases upon detection that the load current has reached a first threshold value.

Abstract: A controller circuit is configured to drive a switching element to establish a channel that electrically couples a source to an inductive element of a buck converter and generate a minimum current sample. In response to current at the switching element exceeding a target peak current threshold of a set of control parameters for the buck converter, the controller circuit is configured to generate a peak current sample, calculate a mean current using the minimum current sample and the peak current sample, and modify the set of control parameters using the mean current. In response to the switching element satisfying an off time of the set of control parameters, the controller circuit is configured to drive the switching element to establish the channel that electrically couples the source to the inductive element during an on state for a subsequent switching period.

Abstract: In one example, a method includes receiving, at a first time by a power switching device via an input connector of the power switching device, a signal that causes the power switching device to output a power signal to a load via an output connector of the power switching device. In this example, a voltage level of the power signal satisfies a voltage threshold at a second time that is later than the first time. In this example, the method also includes communicating, by the power switching device and during a time period between the first time and the second time, with an external device via the input connector.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: In one example, a method includes receiving, at a first time by a power switching device via an input connector of the power switching device, a signal that causes the power switching device to output a power signal to a load via an output connector of the power switching device. In this example, a voltage level of the power signal satisfies a voltage threshold at a second time that is later than the first time. In this example, the method also includes communicating, by the power switching device and during a time period between the first time and the second time, with an external device via the input connector.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.

Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.