Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.

Abstract: A device comprises a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter, and two distinct and parallel sampling channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two sampling channels each comprise an analog-to-digital converter and a Viterbi detector arranged in series and operating according to sampling sequences that alternate with one another.

Abstract: The invention relates to a basic cell for comparing a first and a second digital signal, of the type having at least a first and a second input and a first and a second output and comprising at least one logic gate receiving digital signals at a first and a second signal input, and which comprises at least a first and a second controlled switch inserted in parallel with each other between the output terminal of the logic gate and the second output from the cell, the first switch being also connected between the first input and the first output of the cell and the second switch being also connected between the second input and the second output of the cell. The invention also relates to a digital comparator comprising a plurality of basic cells according to the invention.

Abstract: A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.

Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.

Abstract: A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder.

Abstract: A decoder of a coded serial stream of digital data in a stream of decoded NRZ data has re-timing (BB, AA) flip-flops and a 2.times.1 multiplexer (MUX OUT) selectably providing a single-bit NRZ output stream or a dual-bit (NRZ0 and NRZ1) output streams, by exploiting the predecoded values (ND0 and ND1) produced by two decoding combinative logic networks (RC1 and RC2) that compose the decoder.