Patents by Inventor Paolo Gargini

Paolo Gargini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making EPROM cell with reduced programming voltage
    Patent number: 4519849
    Abstract: An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.
    Type: Grant
    Filed: July 22, 1983
    Date of Patent: May 28, 1985
    Assignee: Intel Corporation
    Inventors: George J. Korsh, Mark A. Holler, George Perlegos, Paolo Gargini
  • Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
    Patent number: 4441247
    Abstract: A process is described for forming MOS circuits which include underlying polysilicon members such as gate members covered with metal. In one embodiment, a self-aligning tungsten process is used to cover the polysilicon members. Low temperature "rear end" steps are used to prevent deterioration of the underlying metal. For example, a plasma nitride protective layer is used to cover the metal. The polysilicon/metal members provide reduced resistance and increase the speed of the resultant MOS circuits.
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: April 10, 1984
    Assignee: Intel Corporation
    Inventors: Paolo Gargini, Israel Beinglass, Norman Ahlquist
  • EPROM Cell with reduced programming voltage and method of fabrication
    Patent number: 4412310
    Abstract: An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.
    Type: Grant
    Filed: October 14, 1980
    Date of Patent: October 25, 1983
    Assignee: Intel Corporation
    Inventors: George J. Korsh, Mark A. Holler, George Perlegos, Paolo Gargini