Abstract: An improved single error correction circuit for a system memory storing in each of its addressable locations a data word and a corresponding error correcting code, which when read out from memory are fed to a syndrome generator which generates in output an error syndrome indication, comprising a set of registers arranged in banks, a first register in each bank for storing a prefixed portion of the data word read out from memory, the other registers in each bank for storing all the possible data configuration obtained from the prefixed portion of the data word stored in the first register of the same bank by inverting one data bit, so that a corrected read out data word is available in such registers in advance of syndrome indication which decoded, provides selection signal enabling one selected register per each bank to output, with minimum delay the latched portion of the data word.