Patents by Inventor Paolo Miliozzi

Paolo Miliozzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for predictive multi-component circuit layout generation with reduced design cycle
    Patent number: 6839887
    Abstract: One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: January 4, 2005
    Assignee: Conexant Systems, Inc.
    Inventors: Koen Lampaer, Andy Brotman, Paolo Miliozzi, Paramjit Singh, Mishel Matloubian, Bijan Bhattacharyya
  • Method and system for predictive MOSFET layout generation with reduced design cycle
    Patent number: 6728942
    Abstract: In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 27, 2004
    Assignee: Conexant Systems, Inc.
    Inventors: Koen Lampaert, Andy Brotman, Paolo Miliozzi, Paramjit Singh, Mishel Matloubian, Bijan Bhattacharyya
  • Method and system for predictive layout generation for inductors with reduced design cycle
    Patent number: 6588002
    Abstract: In one embodiment, a number of parameter values for an inductor, such as a spiral inductor, are received. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor. An inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and, there is no need to extract the internal parasitics of the inductor for further circuit simulations.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 1, 2003
    Assignee: Conexant Systems, Inc.
    Inventors: Koen Lampaert, Andy Brotman, Paolo Miliozzi, Paramjit Singh, Mishel Matloubian, Bijan Bhattacharyya, Francis M Rotella, Rajesh Divecha
  • Method and system for pedictive MOSFET layout generation with reduced design cycle
    Publication number: 20020188920
    Abstract: In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 12, 2002
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Koen Lampaert, Andy Brotman, Paolo Miliozzi, Paramjit Singh, Mishel Matloubian, Bijan Bhattacharyya