Abstract: A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal.

Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal.

Abstract: An interface device having a first and second data terminal configured for the communication of data in duplex mode, with one of the first and second data terminals always assigned to each direction of the communication, the first and second data terminals configurable during operation such that, in a first mode of operation, the first data terminal is configured to send but not to receive data and the second data terminal is configured to receive but not send data, while in a second mode of operation the first data terminal is configured to receive but not to send data and the second data terminal is configured to send but not to receive data.