Patents by Inventor Paparao S. Kavalipati

Paparao S. Kavalipati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power state transition verification for electronic design
    Patent number: 8839164
    Abstract: Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that check if the power domains are active at appropriate times is generated. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 16, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Paparao S. Kavalipati, Andrew Seawright
  • Power State Transition Verification For Electronic Design
    Publication number: 20130232460
    Abstract: Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that check if the power domains are active at appropriate times is generated. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 5, 2013
    Inventors: Paparao S. Kavalipati, Andrew Seawright