Patents by Inventor Parag Banerjee

Parag Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240342090
    Abstract: A method to coat active pharmaceutical ingredient (API) powders with atomically thin layers of biocompatible metal oxide films such as aluminum oxide and zinc oxide films. Metal oxide films provide a barrier that controllably dissolves and releases the active pharmaceutical ingredients (APIs) in different pH environments such as is found in the human gastrointestinal (GI) tract. Coated API powders, can be prepared using the described methods, such as 5-Aminosalicylic acid (5-ASA) powder coated with aluminum oxide and zinc oxide films.
    Type: Application
    Filed: February 16, 2024
    Publication date: October 17, 2024
    Applicant: University of Central Florida Research Foundation, Inc.
    Inventors: Parag Banerjee, Jaynlynn Sosa
  • Publication number: 20240271274
    Abstract: A ceria heterostructure may include one or more base materials and one or more ceria surface structures at least partially surrounding the one or more base materials, where defect states of the one or more ceria surface structures are reversibly controllable by controlling a stress on the one or more surface structures that is at least partially induced by the one or more base materials.
    Type: Application
    Filed: January 12, 2024
    Publication date: August 15, 2024
    Inventors: Sudipta Seal, Parag Banerjee, Udit Kumar
  • Patent number: 11094881
    Abstract: Perovskite films are known to be useful in many different technologies, including solar panels and memristors. Most perovskites contain lead which is undesirable for many reasons. It has been found that bismuth can be used in place of lead in preparing perovskite thin films. Additionally, when chemical vapor deposition is used to prepare the films instead of traditional solution phase methods, the films show greatly improved performance in electronic applications. Additionally, the present disclosure is directed to the use of perovskites in memory devices.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Washington University
    Inventors: Parag Banerjee, Peifu Cheng, Xiao Chen, Yoon Myung
  • Publication number: 20190074439
    Abstract: Perovskite films are known to be useful in many different technologies, including solar panels and memristors. Most perovskites contain lead which is undesirable for many reasons. It has been found that bismuth can be used in place of lead in preparing perovskite thin films. Additionally, when chemical vapor deposition is used to prepare the films instead of traditional solution phase methods, the films show greatly improved performance in electronic applications. Additionally, the present disclosure is directed to the use of perovskites in memory devices.
    Type: Application
    Filed: August 24, 2018
    Publication date: March 7, 2019
    Applicant: Washington University
    Inventors: Parag Banerjee, Peifu Cheng, Xiao Chen, Yoon Myung
  • Patent number: 10032569
    Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: July 24, 2018
    Assignee: UNIVERSITY OF MARYLAND, COLLEGE PARK
    Inventors: Gary W. Rubloff, Sang Bok Lee, Israel Perez, Laurent Lecordier, Parag Banerjee, Chanyuan Liu, Xinyi Chen, Eleanor Gillette
  • Publication number: 20150200058
    Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.
    Type: Application
    Filed: December 15, 2014
    Publication date: July 16, 2015
    Inventors: Gary W. RUBLOFF, Sang Bok LEE, Israel PEREZ, Laurent LECORDIER, Parag BANERJEE, Chanyuan Liu, Xinyi Chen, Eleanor Gillette
  • Patent number: 8912522
    Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 16, 2014
    Assignee: University of Maryland
    Inventors: Gary W. Rubloff, Sang Bok Lee, Israel Perez, Laurent Lecordier, Parag Banerjee
  • Patent number: 8378333
    Abstract: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: February 19, 2013
    Assignee: University of Maryland
    Inventors: Parag Banerjee, Sang Bok Lee, Israel Perez, Erin Robertson, Gary W. Rubloff
  • Patent number: 8374037
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Publication number: 20120280209
    Abstract: An electro-optical device includes a substrate on which first and second electrodes are formed. A plurality of nanoparticles are arrayed on the surface of the substrate between the first and second electrodes. The arrayed nanoparticles exhibit plasmonic activity in at least one wavelength band. A plurality of linking molecules are coupled between respective adjacent ones of the nanoparticles and between each of the electrodes and nanoparticles that are adjacent to the electrodes. The linking molecules are selected to exhibit photo-activity that is complementary to the arrayed nanoparticles.
    Type: Application
    Filed: October 25, 2010
    Publication date: November 8, 2012
    Applicant: The Trustees of the University of Pennsylvania
    Inventors: Dawn Bonnell, Parag Banerjee, David Conklin, Sanjini Nanayakkara
  • Publication number: 20110273929
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Application
    Filed: July 20, 2011
    Publication date: November 10, 2011
    Inventors: Parag BANERJEE, Terry GAFRON, Fernando GONZALEZ
  • Patent number: 7995402
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Publication number: 20110080783
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Application
    Filed: December 13, 2010
    Publication date: April 7, 2011
    Inventors: Parag Banerjee, Terry Grafron, Fernando Gonzalez
  • Publication number: 20110073827
    Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 31, 2011
    Applicant: UNIVERSITY OF MARYLAND
    Inventors: Gary W. RUBLOFF, Sang Bok LEE, Israel PEREZ, Laurent LECORDIER, Parag BANERJEE
  • Patent number: 7852668
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: December 14, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Publication number: 20090129167
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Application
    Filed: January 27, 2009
    Publication date: May 21, 2009
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Publication number: 20090108252
    Abstract: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 30, 2009
    Inventors: Parag Banerjee, Sang Bok Lee, Israel Perez, Erin Robertson, Gary W. Rubloff
  • Patent number: 7486550
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: February 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Publication number: 20070279977
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez