Patents by Inventor Parag Banerjee
Parag Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240342090Abstract: A method to coat active pharmaceutical ingredient (API) powders with atomically thin layers of biocompatible metal oxide films such as aluminum oxide and zinc oxide films. Metal oxide films provide a barrier that controllably dissolves and releases the active pharmaceutical ingredients (APIs) in different pH environments such as is found in the human gastrointestinal (GI) tract. Coated API powders, can be prepared using the described methods, such as 5-Aminosalicylic acid (5-ASA) powder coated with aluminum oxide and zinc oxide films.Type: ApplicationFiled: February 16, 2024Publication date: October 17, 2024Applicant: University of Central Florida Research Foundation, Inc.Inventors: Parag Banerjee, Jaynlynn Sosa
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Publication number: 20240271274Abstract: A ceria heterostructure may include one or more base materials and one or more ceria surface structures at least partially surrounding the one or more base materials, where defect states of the one or more ceria surface structures are reversibly controllable by controlling a stress on the one or more surface structures that is at least partially induced by the one or more base materials.Type: ApplicationFiled: January 12, 2024Publication date: August 15, 2024Inventors: Sudipta Seal, Parag Banerjee, Udit Kumar
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Patent number: 11094881Abstract: Perovskite films are known to be useful in many different technologies, including solar panels and memristors. Most perovskites contain lead which is undesirable for many reasons. It has been found that bismuth can be used in place of lead in preparing perovskite thin films. Additionally, when chemical vapor deposition is used to prepare the films instead of traditional solution phase methods, the films show greatly improved performance in electronic applications. Additionally, the present disclosure is directed to the use of perovskites in memory devices.Type: GrantFiled: August 24, 2018Date of Patent: August 17, 2021Assignee: Washington UniversityInventors: Parag Banerjee, Peifu Cheng, Xiao Chen, Yoon Myung
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Publication number: 20190074439Abstract: Perovskite films are known to be useful in many different technologies, including solar panels and memristors. Most perovskites contain lead which is undesirable for many reasons. It has been found that bismuth can be used in place of lead in preparing perovskite thin films. Additionally, when chemical vapor deposition is used to prepare the films instead of traditional solution phase methods, the films show greatly improved performance in electronic applications. Additionally, the present disclosure is directed to the use of perovskites in memory devices.Type: ApplicationFiled: August 24, 2018Publication date: March 7, 2019Applicant: Washington UniversityInventors: Parag Banerjee, Peifu Cheng, Xiao Chen, Yoon Myung
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Patent number: 10032569Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.Type: GrantFiled: December 15, 2014Date of Patent: July 24, 2018Assignee: UNIVERSITY OF MARYLAND, COLLEGE PARKInventors: Gary W. Rubloff, Sang Bok Lee, Israel Perez, Laurent Lecordier, Parag Banerjee, Chanyuan Liu, Xinyi Chen, Eleanor Gillette
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Publication number: 20150200058Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube or microtube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical device can include a column disposed in a template material extending from one side of the template material to the other side of the template material. Further, the device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed in the column. A variety of configurations, variations, and modifications are provided.Type: ApplicationFiled: December 15, 2014Publication date: July 16, 2015Inventors: Gary W. RUBLOFF, Sang Bok LEE, Israel PEREZ, Laurent LECORDIER, Parag BANERJEE, Chanyuan Liu, Xinyi Chen, Eleanor Gillette
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Patent number: 8912522Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.Type: GrantFiled: August 26, 2010Date of Patent: December 16, 2014Assignee: University of MarylandInventors: Gary W. Rubloff, Sang Bok Lee, Israel Perez, Laurent Lecordier, Parag Banerjee
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Patent number: 8378333Abstract: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.Type: GrantFiled: September 26, 2008Date of Patent: February 19, 2013Assignee: University of MarylandInventors: Parag Banerjee, Sang Bok Lee, Israel Perez, Erin Robertson, Gary W. Rubloff
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Patent number: 8374037Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: GrantFiled: July 20, 2011Date of Patent: February 12, 2013Assignee: Micron Technology, Inc.Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
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Publication number: 20120280209Abstract: An electro-optical device includes a substrate on which first and second electrodes are formed. A plurality of nanoparticles are arrayed on the surface of the substrate between the first and second electrodes. The arrayed nanoparticles exhibit plasmonic activity in at least one wavelength band. A plurality of linking molecules are coupled between respective adjacent ones of the nanoparticles and between each of the electrodes and nanoparticles that are adjacent to the electrodes. The linking molecules are selected to exhibit photo-activity that is complementary to the arrayed nanoparticles.Type: ApplicationFiled: October 25, 2010Publication date: November 8, 2012Applicant: The Trustees of the University of PennsylvaniaInventors: Dawn Bonnell, Parag Banerjee, David Conklin, Sanjini Nanayakkara
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Publication number: 20110273929Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Inventors: Parag BANERJEE, Terry GAFRON, Fernando GONZALEZ
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Patent number: 7995402Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: GrantFiled: December 13, 2010Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
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Publication number: 20110080783Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: ApplicationFiled: December 13, 2010Publication date: April 7, 2011Inventors: Parag Banerjee, Terry Grafron, Fernando Gonzalez
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Publication number: 20110073827Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.Type: ApplicationFiled: August 26, 2010Publication date: March 31, 2011Applicant: UNIVERSITY OF MARYLANDInventors: Gary W. RUBLOFF, Sang Bok LEE, Israel PEREZ, Laurent LECORDIER, Parag BANERJEE
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Patent number: 7852668Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: GrantFiled: January 27, 2009Date of Patent: December 14, 2010Assignee: Micron Technology, Inc.Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
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Publication number: 20090129167Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: ApplicationFiled: January 27, 2009Publication date: May 21, 2009Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
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Publication number: 20090108252Abstract: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.Type: ApplicationFiled: September 26, 2008Publication date: April 30, 2009Inventors: Parag Banerjee, Sang Bok Lee, Israel Perez, Erin Robertson, Gary W. Rubloff
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Patent number: 7486550Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: GrantFiled: June 6, 2006Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
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Publication number: 20070279977Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.Type: ApplicationFiled: June 6, 2006Publication date: December 6, 2007Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez