Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

Abstract: A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.

Abstract: A method for performing verification is disclosed. In response to determining that a log replay module operating in a replay mode has received a command from a testcase that is not equal to a next command in a replay log, a determination is made whether the command is a create relay checkpoint command with a testcase parameter matching a model checkpoint file. In response to determining that the command from the testcase is the create replay checkpoint command with the testcase parameter matching the model checkpoint file, the model checkpoint file is loaded into the simulator, and one or more items of cycle information of the simulator are set to information corresponding to the model checkpoint file.

Abstract: An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

Abstract: The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.