Abstract: Provided is a computer-implemented method for authenticating a customer during payment transactions based on biometric identification parameters of the customer that includes receiving image data associated with an image template for identification of a customer, receiving image data associated with an image of a biometric identification parameter of the customer during a payment transaction between the customer and a merchant, establishing a short-range communication connection with a user device associated with the customer during the payment transaction between the customer and the merchant, authenticating an identity of the customer for the payment transaction via the short-range communication connection, determining an account identifier of an account of the customer based on authenticating the identity of the customer for the payment transaction, and processing the payment transaction using the account identifier of the account of the customer. A system and computer program product are also disclosed.

Abstract: Provided is a computer-implemented method for authenticating a customer during payment transactions based on biometric identification parameters of the customer that includes receiving image data associated with an image template for identification of a customer, receiving image data associated with an image of a biometric identification parameter of the customer during a payment transaction between the customer and a merchant, establishing a short-range communication connection with a user device associated with the customer during the payment transaction between the customer and the merchant, authenticating an identity of the customer for the payment transaction via the short-range communication connection, determining an account identifier of an account of the customer based on authenticating the identity of the customer for the payment transaction, and processing the payment transaction using the account identifier of the account of the customer. A system and computer program product are also disclosed.

Abstract: Provided is a computer-implemented method for authenticating a customer during payment transactions based on biometric identification parameters of the customer that includes receiving image data associated with an image template for identification of a customer, receiving image data associated with an image of a biometric identification parameter of the customer during a payment transaction between the customer and a merchant, establishing a short-range communication connection with a user device associated with the customer during the payment transaction between the customer and the merchant, authenticating an identity of the customer for the payment transaction via the short-range communication connection, determining an account identifier of an account of the customer based on authenticating the identity of the customer for the payment transaction, and processing the payment transaction using the account identifier of the account of the customer. A system and computer program product are also disclosed.

Abstract: Provided is a computer-implemented method for authenticating a customer during payment transactions based on biometric identification parameters of the customer that includes receiving image data associated with an image template for identification of a customer, receiving image data associated with an image of a biometric identification parameter of the customer during a payment transaction between the customer and a merchant, establishing a short-range communication connection with a user device associated with the customer during the payment transaction between the customer and the merchant, authenticating an identity of the customer for the payment transaction via the short-range communication connection, determining an account identifier of an account of the customer based on authenticating the identity of the customer for the payment transaction, and processing the payment transaction using the account identifier of the account of the customer. A system and computer program product are also disclosed.

Abstract: Provided is a computer-implemented method for authenticating a customer during payment transactions based on biometric identification parameters of the customer that includes receiving image data associated with an image template for identification of a customer, receiving image data associated with an image of a biometric identification parameter of the customer during a payment transaction between the customer and a merchant, establishing a short-range communication connection with a user device associated with the customer during the payment transaction between the customer and the merchant, authenticating an identity of the customer for the payment transaction via the short-range communication connection, determining an account identifier of an account of the customer based on authenticating the identity of the customer for the payment transaction, and processing the payment transaction using the account identifier of the account of the customer. A system and computer program product are also disclosed.

Abstract: A system and method for converting radiation therapy information into another form, the converted radiation therapy information being placed in a format such that it can be stored in any storage system, including PACS storages systems, irrespective of the implementation of DICOM; the converted radiation therapy information being expressed in a manner that is proportional/equivalent to a standard imaging parameter for CT or PET.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: Embodiments of the present invention provide power flow analysis and may process electrical power distribution system data in real time to calculate load, current, voltage, losses, fault current and other data. The power flow analysis system may include a detailed data model of the electrical power distribution system, and may accept a variety of real time measurement inputs to support its modeling calculations. The power flow analysis system may calculate data of each of the three distribution system power phases independently and include a distribution state estimation module which allows it to incorporate a variety of real time measurements with varying degrees of accuracy, reliability and latency.

Abstract: A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.

Abstract: In one embodiment, an electrical system having an LED array, a first current source connected to provide a first current to the LED array, a current-sense resistor connected to the LED array, a second current source connected to provide a second current to the current-sense resistor, a control processor, and a voltage sensor adapted to provide a corresponding sensor signal to the control processor, wherein the control processor is adapted to control the first and second current sources based on the sensor signal. The first current source having a diode with first and second sides, an inductor connected between a first reference voltage source and a first side of a diode, a capacitor connected between a second side of the diode and a second reference voltage, and a transistor connected between the first side of the diode and the second reference voltage.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: In a preferred embodiment, a battery charging system in the form of an integrated circuit (IC), incorporated in a consumer electronic device, has a charging controller, a charging current generator, a junction temperature sensor, and a device current monitor. The junction temperature sensor provides to the charging controller a measured junction temperature of the IC. The charging current generator utilizes fractional synthesis, which involves regulating the duty cycles of multiple current sources, to achieve increased current resolution. The charging controller regulates the charging current provided by the charging current generator based on the relation of the measured junction temperature to three or more threshold temperatures.

Abstract: A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Abstract: A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having different amounts of delay, and combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle. The delay processor is adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal.

Abstract: Disclosed is a circuit for testing a delay module. An output of a ring oscillator formed with the delay module is transmitted to a counter. The counter generates a plurality of counts, each count associated with a setting of control lines of the delay module. One of the plurality of counts is then compared with a previous one of the plurality of counts.

Abstract: A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.

Abstract: control processor, wherein the control processor is adapted to control the first and second current sources based on the sensor signal. The first current source having a diode with first and second sides, an inductor connected between a first reference voltage source and a first side of a diode, a capacitor connected between a second side of the diode and a second reference voltage, and a transistor connected between the first side of the diode and the second reference voltage.