Patents by Inventor Parag Raval

Parag Raval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power-performance modulation in caches using a smart least recently used scheme
    Patent number: 7689772
    Abstract: The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Satish Damaraju, Subramaniam Maiyuran, Truyen Trinh, Parag Raval, Peter Smith
  • Power-performance modulation in caches using a smart least recently used scheme
    Publication number: 20070260818
    Abstract: The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 8, 2007
    Inventors: Satish Damaraju, Subramaniam Maiyuran, Truyen Trinh, Parag Raval, Peter Smith