Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract: The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes.

Abstract: An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to manufacturing process variations by adding compensation devices to a first inverter stage in the input buffering stage so as to increase noise margin. A hysteresis characteristic is produced by the circuit thus reducing the effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding the possibility of DC current flow in the circuitry.

Abstract: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Abstract: An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to manufacturing process variations by adding compensation devices to a first inverter stage in the input buffering stage so as to increase noise margin. A hysteresis characteristic is produced by the circuit thus reducing the effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding the possibility of DC current flow in the circuitry.

Abstract: The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Abstract: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

Abstract: A compensated Schmitt Trigger circuit for providing a monotonic hysterisis response, the circuit including a plurality of transistors connected in series and coupled to a common input signal at their control inputs, a feedback circuit connected to the output of the plurality of transistors, an inverter coupled to the output of the plurality of transistors and to the feedback circuit for providing a hysterisis response at higher supply voltage, wherein the feedback circuit includes at least one feedback element coupled between the output of said plurality of transistors and input of the inverter for providing a monotonic hysterisis response at the output node of the Schmitt Trigger circuit. The feedback elements are connected/disconnected by control signals that reflect the variations in PVT conditions, and the control signals are derived from the standard Input/Output circuits library for compensation.

Abstract: The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second